Code360 powered by Coding Ninjas X Naukri.com. Code360 powered by Coding Ninjas X Naukri.com
Table of contents
1.
Introduction
2.
CPU control design and io interfaces questions
3.
Frequently Asked Questions
3.1.
What is memory-mapped I/O?
3.2.
What is the difference between simplex and duplex transmission?
3.3.
What exactly are ADC and DAC?
4.
Conclusion
Last Updated: Mar 27, 2024

CPU control design and io-interfaces part - 2

Author Shivani Singh
0 upvote
Master Python: Predicting weather forecasts
Speaker
Ashwin Goyal
Product Manager @

Introduction

The I/O architecture of a computer system serves as its interaction with the outside world. This architecture is intended to provide a methodical means of controlling interaction with the outside world and to provide information to the operating system.  I/O activity must be effectively managed. 

There are three major I/O techniques: I/O that is programmed to occur under the program's direct and continuous control;  interrupt-driven I/O, in which a program issues an I/O command and then waits for a response to continue to execute until the I/O hardware interrupts. 

To move a large block of data, the processor controls an I/O operation. The purpose of I/O modules is to connect to the memory and CPU via the system bus or control switch and to connect to one or more peripheral devices.

In this blog, we will see some more of the important questions of this section. 

CPU control design and io-interfaces part - 2

CPU control design and io interfaces questions

Interface Questions

Now let us discuss some of the important MCQs of this topic. 

1. A CPU generally handles an interrupt by executing an interrupt service routine 

  1. As soon as an interrupt is raised
  2. By checking the interrupt register at the end of the fetch cycle.
  3. By checking the interrupt register after finishing the execution of the current instruction.
  4. By checking the interrupt register at fixed time intervals.
     

Ans: The correct answer is C.

2. Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory-mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory-mapped I/O?

  1. I/O protection is ensured by operating system routine.
  2. I/O protection is ensured by a hardware trap.
  3. I/O protection is ensured during system configuration.
  4. I/O protection is not possible.
     

Ans: The correct answer is option A. 

3. How many 8-bit characters can be transmitted per second over a 9600 baud serial communication link using a parity synchronous mode of transmission with one start bit & Eight data bits, two stop bits, and one parity bit

  1. 600
  2. 800
  3. 876
  4. 1200
     

Ans: The correct answer is option B

4. Which one of the following is true for a CPU having a single interrupt request line and single interrupt grant line?

  1. Neither vectored input nor multiple interrupting devices are possible
  2. Vectored interrupts are not possible but multiple interrupting devices are possible
  3. Vectored interrupts and multiple interrupting devices are both possible
  4. Vectored interrupts are possible but multiple interrupting devices are not possible
     

Ans: The correct answer is option B
5. In serial data transmission, every byte of data is padded with a ‘0′ at the beginning and one or two ‘1′s at the end of the byte because

  1. The receiver is to be synchronized for byte reception
  2. The receiver recovers lost ‘0’ and ‘1’ from these padded bits
  3. Padded bits are useful in parity computation
  4. None of the above 
     

Ans: The correct answer is A.

6. A processor needs software interrupt to

  1. Test the interrupt system of the processor
  2. Implement co-routines
  3. Obtain system services that need the execution of privileged instructions
  4. Return from subroutine 
     

Ans: The correct answer is C.

7. Which of the following is true?

  1. Unless enabled, a CPU will not be able to process interrupts
  2. Loop instructions cannot be interrupted till they complete
  3. A processor checks for interrupts before executing a new instruction
  4. Only level-triggered interrupts are possible on microprocessors
     

Ans: The correct answer is A.

8. Which of the following device should get higher priority in assigning interrupts?

  1. Hard disk
  2. Printer
  3. Keyboard 
  4. Floppy disk 
     

Ans: The correct answer is A

9. The correct matching for the following pairs is

Matching Pairs

  1. a-4,b-3,c-1,d-2
  2. a-2,b-1,c-3,d-4
  3. a-4,b-3,c-2,d-1
  4. a-2,b-3,c-4,d-1
     

Ans: The correct answer is B.

10. It gives non-uniform priority to various devices.

  1. It gives non-uniform parity to various devices.
  2. It gives uniform parity to all devices
  3. It is only useful for connecting slow devices to a processor
  4. It requires a separate interrupt pin on the processor for each device
     

Ans: The correct answer is A

11. In a vectored interrupt

  1. The branch address is assigned to a fixed location in the memory
  2. The interrupting source implies the branch information to the processor through an interrupt vector
  3. The branch address is obtained from registering in a processor 
  4. None of these
     

Ans: The correct answer is B

12. Start and stop bits do not contain 'information' but these are used in serial communication for

  1. Error detection
  2. Error correction
  3. Synchronization
  4. Slowing down the communication
     

Ans: The correct answer is C

13. The following are some events that occur after a device controller issues an interrupt while process L is under execution.

  1.  The processor pushes the process status of L onto the control stack.
  2.  The processor finishes the execution of the current instruction.
  3.  The processor executes the interrupt service routine.
  4.  The processor pops the process status of L from the control stack.
  5.  The processor loads the new PC value based on the interrupt.
     

Which one of the following is the correct order in which the events above occur?

  1. QPTRS
  2. PTRSQ
  3. TRPQS
  4. QTPRS
     

Ans: The correct answer is A

14. On a non-pipe-lined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory. Initialize the address register Initialize the count to 500

LOOP: Load a byte from the device and store it in memory at the address given by the address register

Increment the address register 

Decrement the count 

If count != 0 go to LOOP

Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.

The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speed up when the DMA controller-based design is used in place of the interrupt-driven program-based input-output?

  1. 3.4
  2. 4.4
  3. 5.1
  4. 6.7
     

Ans: The correct answer is A
15. Consider the disk drive with the following specifications 16 surfaces,  512 tracks/surface, 512 sectors/track, 1 KB/sector, and rotation speed of 3000 rpm. The disk is operated in cycle stealing mode whereby whenever the one-byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4-byte word from the memory in each DMA cycle. Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is

  1. 10
  2. 25
  3. 40
  4. 50
     

Ans: The correct answer is B

16. A device with a data transfer rate of 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 μsec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode?

  1. 15
  2. 25
  3. 35
  4. 45
     

Ans: The correct answer is B. 

Get the tech career you deserve, faster!
Connect with our expert counsellors to understand how to hack your way to success
User rating 4.7/5
1:1 doubt support
95% placement record
Akash Pal
Senior Software Engineer
326% Hike After Job Bootcamp
Himanshu Gusain
Programmer Analyst
32 LPA After Job Bootcamp
After Job
Bootcamp

Frequently Asked Questions

What is memory-mapped I/O?

It is one of the methods for connecting I/O devices to μp. Memory-mapped I/O assigns and identifies I/O devices with 16-bit addresses. Memory-related instructions (such as LDA, STA, and so on) and memory control signals (MEMR, MEMW) are used to transfer data between MPU and I/O devices.

What is the difference between simplex and duplex transmission?

Simplex transmission means that data is sent in only one direction. Data flows in both directions during duplex transmission. If the transmission is only one way, it is called half-duplex; if it is both ways at the same time, it is called full-duplex.

What exactly are ADC and DAC?

Analog-to-digital converter refers to an electronic circuit that converts an analog signal to a digital signal (ADC).

A digital-to-analog converter is an electronic circuit that converts a digital signal to an analog signal (DAC).

Conclusion

To conclude this blog, we discussed all the important multiple choice questions regarding the CPU control design and io interfaces. 

Do upvote our blogs if you find them helpful and engaging!

Happy Learning!

Previous article
CPU control design and io-interfaces
Next article
Computer Arithmetic
Live masterclass