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Last Updated: Mar 25, 2025
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Instruction Format in Computer Architecture

Author Kushleen Waraich
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Introduction  

Instruction formats in computer architecture refer to the way instructions are encoded and represented in Machine Language. Types of instruction formats in computer architecture are:, zero, one, two, and three-address instructions.

A computer program is a set of instructions that suggests the computer to perform a specific task. A computer program can contain multiple statements. The instruction length is generally multiples of the character length (8 bits).

instruction format in computer architecture

First, let us recall and discuss some important concepts related to Instruction Format in Computer Architecture:

  1. Instruction includes a set of operational codes, operands, opcode, and addressing mode.
     
  2. Instruction length is the most fundamental issue of the format design. The longer the instruction, the longer will be the time taken to fetch the instruction.
     
  3. The number of bits is directly proportional to the memory range. i.e., the larger the range requirement, the more number bits will be required.
     
  4. If a system supports the virtual memory, then the memory range that needs to be addressed by the instruction will be larger than the physical memory.
     
  5. Instruction length should be equal to or the multiple of data bus length.
     

Recommended Topic - Memory hierarchy in computer network 

What is Instruction Format in Computer Architecture?

The instruction formats are a sequence of bits (0 and 1). These bits, when grouped, are known as fields. Each field of the machine provides specific information to the CPU related to the operation and location of the data. 

The instruction format also defines the layout of the bits for an instruction. It can be of variable lengths with multiple numbers of addresses. These address fields in the instruction format vary as per the organization of the registers in the CPU. The formats supported by the CPU depend upon the Instructions Set Architecture implemented by the processor. 

Depending on the multiple address fields, the instruction is categorized as follows:

  1. Three address instruction
  2. Two address instruction
  3. One address instruction
  4. Zero address instruction


The operations specified by a computer instruction are executed on data stored in memory or processor registers. The operands residing in processor registers are specified with an address. The registered address is a binary number of k bits that defines one of the 2k registers in the CPU. Thus, a CPU with 16 processors registers R0 through R15 and will have a four-bit register address field. 

Example: The binary number 0011 will designate register R3.

 

A computer can have instructions of different lengths containing varying numbers of addresses. The number of address fields of a computer depends on the internal design of its registers. Most of the computers fall into one of three types of CPU organizations:

  1. Single accumulator organization.
  2. General register organization.
  3. Stack organization.

1. Single Accumulator Organization

All the operations on a system are performed with an implied accumulator register. The instruction format in this type of computer uses one address field. 

For example, the instruction for arithmetic addition is defined by an assembly language instruction ‘ADD.’ 

Where X is the operand’s address, the ADD instruction results in the operation. 

AC ← AC + M[X].

AC is the accumulator register, M[X] symbolizes the memory word located at address X. 

2. General Register Organization

The general register type computers employ two or three address fields in their instruction format. Each address field specifies a processor register or a memory. An instruction symbolized by ADD R1, X specifies the operation R1 ← R + M [X]. 

This instruction has two address fields: register R1 and memory address X.  

3. Stack Organization

A computer with a stack organization has PUSH and POP instructions that require an address field.  Hence, the instruction PUSH X pushes the word at address X to the top of the stack. The stack pointer updates automatically. In stack-organized computers, the operation type instructions don’t require an address field as the operation is performed on the two items on the top of the stack. 

Types of Instruction Formats

1. Zero Address Instruction

This instruction does not have an operand field, and the location of operands is implicitly represented. The stack-organized computer system supports these instructions. To evaluate the arithmetic expression, it is required to convert it into reverse polish notation.

Zero Address Instruction

Example: Consider the below operations, which shows how X = (A + B) ∗ (C + D) expression will be written for a stack-organized computer. 

TOS: Top of the Stack
PUSH       	A 		TOS ← A
PUSH      	B     	TOS ← B
ADD          			TOS ← (A + B)
PUSH       	C     	TOS ← C
PUSH		D     	TOS ← D
ADD				TOS ← (C + D)
MUL				TOS ← (C + D) ∗ (A + B)
POP		X     		M [X] ← TOS

2. One Address Instruction

This instruction uses an implied accumulator for data manipulation operations. An accumulator is a register used by the CPU to perform logical operations. In one address instruction, the accumulator is implied, and hence, it does not require an explicit reference. For multiplication and division, there is a need for a second register. However, here we will neglect the second register and assume that the accumulator contains the result of all the operations.

One address Instruction

Example: The program to evaluate X = (A + B) ∗ (C + D) is as follows: 

LOAD		A		AC ← M [A]
ADD		B		AC ← A [C] + M [B] 
STORE		T		M [T] ← AC 
LOAD		C		AC ← M [C] 
ADD		D		AC ← AC + M [D] 
MUL		T		AC ← AC ∗ M [T] 
STORE		X		M [X] ← AC

 

All operations are done between the accumulator(AC) register and a memory operand.

M[ ] is any memory location.  

M[T] addresses a temporary memory location for storing the intermediate result. 

This instruction format has only one operand field. This address field uses two special instructions to perform data transfer, namely:

  • LOAD: This is used to transfer the data to the accumulator.
  • STORE: This is used to move the data from the accumulator to the memory.

3. Two Address Instructions

This instruction is most commonly used in commercial computers. This address instruction format has three operand fields. The two address fields can either be memory addresses or registers. 

two address instructions

Example: The program to evaluate X = (A + B) ∗ (C + D) is as follows: 

MOV		R1, A		R1 ← M [A]
ADD		R1, B		R1 ← R1 + M [B]
MOV		R2, C		R2 ← M [C]
ADD		R2, D		R2 ← R2 + M [D]
MUL		R1, R2		R1 ← R1∗R2
MOV		X, R1		M [X] ← R1

The MOV instruction transfers the operands to the memory from the processor registers. R1, R2 registers.

4. Three Address Instruction

The format of a three address instruction requires three operand fields. These three fields can be either memory addresses or registers.

three address instructions

Example: The program in assembly language X = (A + B) ∗ (C + D) Consider the instructions given below that explain each instruction's register transfer operation.

ADD 	R1, A, B     	R1 ← M [A] + M [B] 
ADD   	R2, C, D    	R2 ← M [C] + M [D] 
MUL   	X, R1, R2    	M [X] ← R1 ∗ R2

 

Two processor registers, R1 and R2. 

The symbol M [A] denotes the operand at memory address symbolized by A. The operand1 and operand2 contain the data or address that the CPU will operate. Operand 3 contains the result’s address.

Advantages of Zero-Address, One-Address, Two-Address, and Three-Address Instructions

1. Zero-Address Instructions

  • Efficient Stack-Based Execution – Uses implicit operands stored in a stack, reducing instruction size.
  • Faster Execution – Eliminates the need for address specification, making operations quicker.
  • Simplified Instruction Format – No need for operand fields, making instruction decoding easier.

2. One-Address Instructions

  • Smaller Instruction Size – Requires only one address, reducing memory consumption.
  • Simplifies Register Use – Uses the accumulator as the default operand, reducing operand management complexity.
  • Efficient for Simple Computations – Well-suited for operations that rely on a single register.

3. Two-Address Instructions

  • More Flexibility in Computation – Allows operations between two different locations.
  • Fewer Instructions Required – Reduces the number of instructions compared to one-address systems.
  • Better Use of Registers – Provides more direct register manipulation than one-address formats.

4. Three-Address Instructions

  • High Computational Efficiency – Allows complex expressions to be evaluated in fewer steps.
  • Improved Parallelism – Supports instruction-level parallelism in modern CPUs.
  • Reduced Need for Extra Memory Operations – Eliminates unnecessary data transfers by directly specifying three operands.

Disadvantages of Zero-Address, One-Address, Two-Address, and Three-Address Instructions

1. Zero-Address Instructions

  • Limited Flexibility – Stack-based operations require strict order execution.
  • Increased Overhead – Requires additional push and pop operations, adding execution overhead.
  • Not Suitable for All Architectures – Most modern CPUs are register-based rather than stack-based.

2. One-Address Instructions

  • Frequent Memory Access – Since only one address is available, memory must be accessed repeatedly for intermediate results.
  • Slower Execution for Complex Operations – Requires multiple instructions to complete a single computation.
  • Limited Optimization Opportunities – Cannot efficiently exploit modern CPU features like parallelism.

3. Two-Address Instructions

  • Higher Instruction Count – Requires additional instructions to store results, increasing execution time.
  • Memory Utilization Overhead – Since one operand is usually overwritten, extra memory management is needed.
  • Not Ideal for Complex Computations – May require additional temporary registers for multi-step calculations.

4. Three-Address Instructions

  • Larger Instruction Size – Requires more bits for specifying three addresses, increasing memory usage.
  • Complex Instruction Decoding – Needs more processing power for instruction decoding.
  • Increased CPU Hardware Complexity – Requires additional logic in the CPU to handle multiple addresses.

Frequently Asked Questions

What are the 3 types of instruction format?

The three types of instruction formats in computer architecture are zero, one and two address instruction formats.

What is an example of an instruction format?

An example of an instruction format is the MIPS architecture's R-type format, which includes fields for opcode, source registers, destination register, shift amount, and function code.

What are the different fields of instruction?

An instruction consists of fields like Opcode (operation to perform), Address field (operand location), Mode field (addressing method), Register field (registers used), Immediate field (constant values), Condition Code field (status flags), and Jump field (branching address).

Conclusion

This blog discussed instruction formats and their types. The instruction formats are a sequence of bits (0 and 1). The instruction format also defines the layout of the bits for an instruction. It can be of variable lengths with multiple numbers of addresses. 

To learn more about Micro Operations, refer to Arithmetic Micro Operations.

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