Introduction
Instruction formats in computer architecture refer to the way instructions are encoded and represented in Machine Language. Types of instruction formats in computer architecture are:, zero, one, two, and three-address instructions.
A computer program is a set of instructions that suggests the computer to perform a specific task. A computer program can contain multiple statements. The instruction length is generally multiples of the character length (8 bits).
First, let us recall and discuss some important concepts related to Instruction Format in Computer Architecture:
- Instruction includes a set of operational codes, operands, opcode, and addressing mode.
- Instruction length is the most fundamental issue of the format design. The longer the instruction, the longer will be the time taken to fetch the instruction.
- The number of bits is directly proportional to the memory range. i.e., the larger the range requirement, the more number bits will be required.
- If a system supports the virtual memory, then the memory range that needs to be addressed by the instruction will be larger than the physical memory.
- Instruction length should be equal to or the multiple of data bus length.
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What is Instruction Format in Computer Architecture?
The instruction formats are a sequence of bits (0 and 1). These bits, when grouped, are known as fields. Each field of the machine provides specific information to the CPU related to the operation and location of the data.
The instruction format also defines the layout of the bits for an instruction. It can be of variable lengths with multiple numbers of addresses. These address fields in the instruction format vary as per the organization of the registers in the CPU. The formats supported by the CPU depend upon the Instructions Set Architecture implemented by the processor.
Depending on the multiple address fields, the instruction is categorized as follows:
- Three address instruction
- Two address instruction
- One address instruction
- Zero address instruction
The operations specified by a computer instruction are executed on data stored in memory or processor registers. The operands residing in processor registers are specified with an address. The registered address is a binary number of k bits that defines one of the 2k registers in the CPU. Thus, a CPU with 16 processors registers R0 through R15 and will have a four-bit register address field.
Example: The binary number 0011 will designate register R3.
A computer can have instructions of different lengths containing varying numbers of addresses. The number of address fields of a computer depends on the internal design of its registers. Most of the computers fall into one of three types of CPU organizations:
- Single accumulator organization.
- General register organization.
- Stack organization.
1. Single Accumulator Organization
All the operations on a system are performed with an implied accumulator register. The instruction format in this type of computer uses one address field.
For example, the instruction for arithmetic addition is defined by an assembly language instruction ‘ADD.’
Where X is the operand’s address, the ADD instruction results in the operation.
AC ← AC + M[X].
AC is the accumulator register, M[X] symbolizes the memory word located at address X.
2. General Register Organization
The general register type computers employ two or three address fields in their instruction format. Each address field specifies a processor register or a memory. An instruction symbolized by ADD R1, X specifies the operation R1 ← R + M [X].
This instruction has two address fields: register R1 and memory address X.
3. Stack Organization
A computer with a stack organization has PUSH and POP instructions that require an address field. Hence, the instruction PUSH X pushes the word at address X to the top of the stack. The stack pointer updates automatically. In stack-organized computers, the operation type instructions don’t require an address field as the operation is performed on the two items on the top of the stack.