JK flip flop - Diagram, Full Form, Tables, Equation

Master-Slave JK Flip-flop

Basically, a master-slave flip-flop is a system of two flip flops—one being designated as the master and the other being the slave. The figure III below shows that a clock pulse is applied to the master, and the inverted form of the same clock pulse is applied to the slave. When    CLK = 1, the first flip-flop (i.e., the master) is enabled, and the outputs Qm and Q'm respond to the inputs J and K according to the table shown.

At this time, the second flip flop (i.e., the slave) is disabled because the CLK is LOW to the second flip flop. Similarly, when CLK becomes LOW, the master becomes disabled, and when the slave becomes active. Therefore, the outputs Q and Q' follow the outputs Qm and Q'm respectively.

Since the second flip-flop just follows the first one, it is referred to as a slave, and the first one is called the master. Hence, the configuration is referred to as a master-slave (M-S) flip-flop. 

Fig I

Fig II

Fig III

The state of the master-slave flip-flop, shown in the figure given above, changes at the negative transition (trailing edge) of the clock pulse. Hence, it becomes negative triggering a master-slave flip-flop. This can be changed to a positive edge triggering flip-flop by adding two inverters to the system - one before the clock pulse is applied to the master and an additional one in between the master and the slave. 

The logic symbol of a negative edge master-slave is shown in the figure given below. The system of master-slave flip-flops is not restricted to J-K master-slave only. There may be an S-R master-slave or a D master-slave, etc., in all of them the slave is an S-R flip-flop, whereas the master changes to J-K or S-R or D flip-flops. 

Characteristic Table:

Applications of JK Flip-Flop

• Counters: Used in binary, ripple, and up/down counters due to their ability to toggle states.
   
• Registers: Helps in designing shift registers, which store and shift data in sequential circuits.
   
• Memory Units: Used in RAM and other storage devices to retain binary data.
   
• Frequency Division: Divides input clock frequency by two, making it useful in clock division circuits.
   
• Control Circuits: Utilized in control systems for state transitions and event detection.

Advantages of JK Flip-Flop

• No Invalid State: Unlike the SR flip-flop, the JK flip-flop eliminates the indeterminate state, ensuring reliable operation.
   
• Toggle Feature: It can function as a T flip-flop, making it highly useful in designing counters and frequency dividers.
   
• Versatility: Supports multiple applications in digital circuits, including sequential logic designs, shift registers, and memory units.

Disadvantages of JK Flip-Flop

• Timing Issues: At higher clock speeds, the JK flip-flop can experience race conditions, leading to unstable outputs.
   
• Increased Circuit Complexity: Compared to SR flip-flops, it requires more gates and connections, making implementation more complex.
   
• Power Consumption: More logic elements result in higher power usage, which can be a drawback in low-power applications.

Frequently Asked Questions

What is a clock in a flip flop?

A clock pulse is a time-varying voltage signal that controls a flip flop's operation (triggering). For exp, if a clock pulse is of frequency 1 Hz, the voltage it will supply will oscillate between X Volts and Y Volts(X and Y are any dc voltages), and this change occurs every half second.

What is the status of Q output when J= 1 and k= 0?

If inputs of J and K are both LOW (J = K = 0), there will be no change in Q, no matter how many times the clock pulse is applied. If K = 1 (HIGH) and J = 0 (LOW) the next clock edge resets Q output LOW (Q = 0). If K = 0 and J = 1, then the next clock edge sets Q output HIGH (Q = 1).

How is a J-K flip-flop made to toggle? 

When j=k=1, the race condition occurs, which means both outputs want to be HIGH. Hence, there is a toggle condition where 0 becomes 1 and 1 becomes 0. That is device is either reset or set.

What is the toggle condition?

Condition of a flip-flop circuit in which the internal state of the flip-flop changes from value 0 to 1 or from 1 to 0.

What is J in JK flip-flop?

The JK flip flop was named after Jack Kilby, the Texas Instruments engineer who invented the integrated circuit in 1958. In his honor, the modified RS circuit that eliminated race conditions was named JK.

Conclusion

In this article, we discussed the JK flip-flop, a fundamental sequential circuit widely used in digital electronics. We discussed its working principle, truth table, and characteristic equation. Unlike other flip-flops, the JK flip-flop eliminates the indeterminate state present in the SR flip-flop, making it more reliable for various applications. With its ability to toggle states and store binary information, the JK flip-flop is extensively used in counters, registers, and memory devices. Understanding its operation is essential for designing efficient digital circuits.