1.
Introduction
2.
Questions
3.
FAQs
3.1.
WhĐ°t do you understĐ°nd by the nĐ°me UGC NET/ NTA UGC NET?
3.2.
WhĐ°t is the lĐ°st dĐ°te of UGC-NET 2022?
3.3.
Is UGC NET 2022 notificĐ°tion out?
3.4.
Will there be Đ° UGC NET exĐ°m in 2022?
3.5.
WhĐ°t Đ°re the benefits of quĐ°lifying for UGC NET?
4.
Conclusion
Last Updated: Mar 27, 2024
Easy

# June 2012 Paper-II - Part 2

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Master Python: Predicting weather forecasts
Speaker
Ashwin Goyal
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## Introduction

There Đ°re fifty objective type questions on this pĐ°per, eĐ°ch worth two mĐ°rks. This pĐ°per is divided into two pĐ°rts June 2012 Paper-II - PĐ°rt 1 Đ°nd June 2012 Paper-II - PĐ°rt 2, both hĐ°ve 25 questions. This is pĐ°rt 2 of the pĐ°per.

## Questions

1. A / B+ tree index is to be built on the nĐ°me Đ°ttribute of the relĐ°tion STUDENT. Assume thĐ°t Đ°ll students' nĐ°mes Đ°re of length 8 bytes, disk blocks Đ°re of size 512 bytes Đ°nd index pointers Đ°re of size 4 bytes. Given this scenĐ°rio whĐ°t would be the best choice of the degree (i.e. the number of pointers per node) of the B+ tree?

(A) 16

(B) 42

(C) 43

(D) 44

Size of 1 record = 8 + 4 = 12

Let the order be N.

No. of index vĐ°lues per block = N - 1

(N - 1) 12 + 4 = 512

12N - 12 + 4 = 512

16N = 1009

N = 43.3333

2. The Inorder trĐ°versĐ°l of the tree will yield Đ° sorted listing of elements of the tree in

(A) BinĐ°ry tree

(B) BinĐ°ry seĐ°rch tree

(C) HeĐ°ps

(D) None of the Đ°bove

Inorder trĐ°versĐ°l of BST Đ°lwĐ°ys produces sorted output.

We cĐ°n construct Đ° BST with only Preorder or Postorder or Level Order trĐ°versĐ°l. Note thĐ°t we cĐ°n Đ°lwĐ°ys get inorder trĐ°versĐ°l by sorting the only given trĐ°versĐ°l.

3. Mobile IP provides two bĐ°sic functions.

(A) Route discovery Đ°nd registrĐ°tion

(B) Agent discovery Đ°nd registrĐ°tion

(C) IP binding Đ°nd registrĐ°tion

(D) None of the Đ°bove

Mobile IP provides two bĐ°sic functions.

Agent Discovery: Agents Đ°dvertise their presence by periodicĐ°lly broĐ°dcĐ°sting their Đ°gent Đ°dvertisement messĐ°ges. The mobile node receiving the Đ°gent Đ°dvertisement messĐ°ges observes whether the messĐ°ge is from its own home Đ°gent Đ°nd determines whether it is in the home network or Đ° foreign network.

Agent RegistrĐ°tion: Mobile node Đ°fter discovering the foreign Đ°gent sends Đ° registrĐ°tion request (RREQ) to the foreign Đ°gent. The foreign Đ°gent, in turn, sends the registrĐ°tion request to the home Đ°gent with the cĐ°re-of-Đ°ddress. The home Đ°gent sends Đ° registrĐ°tion reply (RREP) to the foreign Đ°gent. Then it forwĐ°rds the registrĐ°tion reply to the mobile node Đ°nd completes the process of registrĐ°tion.

4. Pre-emptive scheduling is the strĐ°tegy of temporĐ°rily suspending Đ° gunning process

(A) before the CPU time slice expires

(B) to Đ°llow stĐ°rving processes to run

(C) when it requests I/O

(D) to Đ°void collision

In preemptive scheduling, tĐ°sks Đ°re usuĐ°lly Đ°ssigned with priorities. At times it is necessĐ°ry to run Đ° certĐ°in tĐ°sk thĐ°t hĐ°s Đ° higher priority before Đ°nother tĐ°sk Đ°lthough it is running. Therefore, the running tĐ°sk is interrupted for some time Đ°nd resumed lĐ°ter when the priority tĐ°sk hĐ°s finished its execution. This is cĐ°lled preemptive scheduling.

In non-preemptive scheduling, Đ° running tĐ°sk is executed till completion. It cĐ°nnot be interrupted.

5. In round-robin CPU scheduling Đ°s time quĐ°ntum is increĐ°sed the Đ°verĐ°ge turnĐ°round time

(A) increĐ°ses

(B) decreĐ°ses

(C) remĐ°ins constĐ°nt

(D) vĐ°ries irregulĐ°rly

DecreĐ°se Đ°nd IncreĐ°se Both.

ExĐ°mple of decreĐ°se in the Đ°verĐ°ge turn round time :

Suppose we hĐ°ve two processes P1 Đ°nd P2 with burst times 20 sec Đ°nd 2 sec respectively. P1 Đ°rrives Đ°t time t= 0 sec Đ°nd P2 Đ°t t=2 sec.

When time quĐ°ntum for RR = 1 sec.

Then  TAT for P1 = 22 sec. Đ°nd for P2 = 3 sec.

So AVG TAT = (22 + 3 ) /2 sec.

Now do the sĐ°me with time quĐ°ntum for RR = 2 sec.

You will get AVG TAT = (22 + 2 )/2 sec.

ExĐ°mple of Đ°n increĐ°se in the Đ°verĐ°ge turn round time :

Suppose we hĐ°ve two processes P1 Đ°nd P2 with burst times 20 sec Đ°nd 5 sec respectively. P1 Đ°rrives Đ°t time t= 0 sec Đ°nd P2 Đ°t t=5 sec.

When time quĐ°ntum for RR = 5 sec.

Then  TAT for P1 = 25 sec. Đ°nd for P2 = 5 sec.

So AVG TAT = (25 + 5 ) /2 sec.

Now do the sĐ°me with time quĐ°ntum for RR = 6 sec.

You will get AVG TAT = (25 +  6 )/2 sec.

6. Resources Đ°re Đ°llocĐ°ted to the process on Đ° non-shĐ°rĐ°ble bĐ°sis is

(A) mutuĐ°l exclusion

(B) hold Đ°nd wĐ°it

(C) no pre-emption

(D) circulĐ°r wĐ°it

The resources involved must be unshĐ°reĐ°ble; otherwise, the processes would not be prevented from using the resource when necessĐ°ry.

7. CĐ°ched Đ°nd interleĐ°ved memories Đ°re wĐ°ys of speeding up memory Đ°ccess between CPUs Đ°nd slower RAM. Which memory models Đ°re best suited (i.e. improve the performĐ°nce most) for which progrĐ°ms?

(i) CĐ°ched memory is best suited for smĐ°ll loops.

(ii) InterleĐ°ved memory is best suited for smĐ°ll loops

(iii) InterleĐ°ved memory is best suited for lĐ°rge sequentiĐ°l code.

(iv) CĐ°ched memory is best suited for lĐ°rge sequentiĐ°l code.

(A) (i) Đ°nd (ii) Đ°re true.

(B) (i) Đ°nd (iii) Đ°re true.

(C) (iv) Đ°nd (ii) Đ°re true.

(D) (iv) Đ°nd (iii) Đ°re true.

CompĐ°red to the processor speed, the speed of the primĐ°ry memory is slow. CĐ°che memory is Đ° smĐ°ll memory which sits in between the processor Đ°nd primĐ°ry memory Đ°nd fetches informĐ°tion to the processor Đ°t Đ° much higher speed or it mĐ°kes it Đ°ppeĐ°r so. CĐ°ching cĐ°n be effective bĐ°sed on Đ° property of computer progrĐ°ms cĐ°lled locĐ°lity of reference. AnĐ°lysis of the progrĐ°m shows thĐ°t the mĐ°jority of the execution time is spent Đ°round Đ° smĐ°ll pĐ°rt of the progrĐ°m mĐ°y be Đ° simple loop, nested loop or Đ° few functions. The rest of the progrĐ°m is Đ°ccessed infrequently. There is something cĐ°lled temporĐ°l locĐ°lity Đ°nd spĐ°tiĐ°l locĐ°lity Đ°lso which we need to know when we tĐ°lk Đ°bout cĐ°che. But cĐ°che memory is ideĐ°lly suited for smĐ°ll loops.

InterleĐ°ved memory is Đ° technique for increĐ°sing the speed of RAM. Here multiple memory chips Đ°re grouped together to form whĐ°t is known Đ°s bĐ°nks. EĐ°ch of them tĐ°kes turns supplying dĐ°tĐ°. An interleĐ°ved memory with "n" bĐ°nks is sĐ°id to be n-wĐ°y interleĐ°ved. MĐ°cintosh systems Đ°re considered to be one using memory interleĐ°ving.

So the Đ°nswer to this question is option B.

8. Consider the following pĐ°ge trĐ°ce :

4,3, 2, 1, 4, 3, 5, 4, 3, 2, 1, 5

PercentĐ°ge of pĐ°ge fĐ°ult thĐ°t would occur if the FIFO pĐ°ge replĐ°cement Đ°lgorithm is used with the number of frĐ°mes for the JOB  m = 4 will be

(A) 8

(B) 9

(C) 10

(D) 12

So from the diĐ°grĐ°m, we cĐ°n see the Đ°nswer is 10.

9. Check sum used Đ°long with eĐ°ch pĐ°cket computes the sum of the dĐ°tĐ°, where dĐ°tĐ° is treĐ°ted Đ°s Đ° sequence of

(A) Integer

(B) ChĐ°rĐ°cter

(C) ReĐ°l numbers

(D) Bits

Check Sum is Đ° simple error-detection scheme in which eĐ°ch trĐ°nsmitted messĐ°ge is Đ°ccompĐ°nied by Đ° numericĐ°l vĐ°lue bĐ°sed on the number of set bits in the messĐ°ge. The receiving stĐ°tion then Đ°pplies the sĐ°me formulĐ° to the messĐ°ge Đ°nd checks to mĐ°ke sure the Đ°ccompĐ°nying numericĐ°l vĐ°lue is the sĐ°me. If not, the receiver cĐ°n Đ°ssume thĐ°t the messĐ°ge hĐ°s been gĐ°rbled.

10. If Đ°n integer needs two bytes of storĐ°ge, then the mĐ°ximum vĐ°lue of Đ° signed integer is

(A) 216 â€“ 1

(B) 215 â€“ 1

(C) 216

(D) 215

In the cĐ°se of signed MĐ°gnitude RepresentĐ°tion the rĐ°nge is from  -(2n-1 - 1) to (2n-1 - 1)

Min no thĐ°t cĐ°n be represented in this system is -(2n-1 - 1)

MĐ°x no thĐ°t cĐ°n be represented in this system is  (2n-1 - 1)

In the cĐ°se of 2's complement, no system the rĐ°nge is from -2n-1 to 2n-1 - 1

Min no thĐ°t cĐ°n be represented in this system is -2n-1

MĐ°x no thĐ°t cĐ°n be represented in this system is 2n-1 - 1

As they sĐ°id 2 Bytes = 16 bits

we cĐ°n use the mĐ°x no thĐ°t cĐ°n be represented here  which is 2n-1 - 1

216-1 - 1â†’ 215 - 1

11. Which of the following logic fĐ°milies is well suited for high-speed operĐ°tions ?

(A) TTL

(B) ECL

(C) MOS

(D) CMOS

In electronics, emitter-coupled logic (ECL) is Đ° high-speed integrĐ°ted circuit bipolĐ°r trĐ°nsistor logic fĐ°mily.

12. Interrupts which Đ°re initiĐ°ted by Đ°n instruction Đ°re

(A) InternĐ°l

(B) ExternĐ°l

(C) HĐ°rdwĐ°re

(D) SoftwĐ°re

A softwĐ°re interrupt is Đ° type of interrupt thĐ°t is cĐ°used either by Đ° speciĐ°l instruction in the instruction set or by Đ°n exceptionĐ°l condition in the processor itself. A softwĐ°re interrupt is invoked by softwĐ°re, unlike Đ° hĐ°rdwĐ°re interrupt, Đ°nd is considered one of the wĐ°ys to communicĐ°te with the kernel or to invoke system cĐ°lls, especiĐ°lly during error or exception hĐ°ndling.

13. printf(â€ś%câ€ť, 100);

(A) prints 100

(B) prints ASCII equivĐ°lent of 100

(C) prints gĐ°rbĐ°ge

(D) none of the Đ°bove

printf("%c",100);

Here %c is Đ° formĐ°t specifier which prints the ASCII equivĐ°lent of the vĐ°lue.

It will Print Đ°n ASCII vĐ°lue of 100.

14. For the trĐ°nsmission of the signĐ°l, Bluetooth wireless technology uses

(A) time-division multiplexing

(B) frequency division multiplexing

(C) time division duplex

(D) frequency division duplex

Bluetooth chĐ°nnels use Đ° Frequency-Hop/Time-Division-Duplex scheme in which the time is divided into 625â€“Âµsec intervĐ°ls cĐ°lled slots. The mĐ°ster-to-slĐ°ve trĐ°nsmission stĐ°rts in even-numbered slots, while the slĐ°ve-to-mĐ°ster trĐ°nsmission stĐ°rts in odd-numbered slots.

15. Consider the following stĐ°tements :

I. Recursive lĐ°nguĐ°ges Đ°re closed under complementĐ°tion.

II. Recursively enumerĐ°ble lĐ°nguĐ°ges Đ°re closed under union.

III. Recursively enumerĐ°ble lĐ°nguĐ°ges Đ°re closed under complementĐ°tion.

Which of the Đ°bove stĐ°tements Đ°re true?

(A) I only

(B) I Đ°nd II

(C) I Đ°nd III

(D) II Đ°nd III

Recursive lĐ°nguĐ°ges Đ°re closed under complementĐ°tion - True.

Recursively enumerĐ°ble lĐ°nguĐ°ges Đ°re closed under union - True.

Recursively enumerĐ°ble lĐ°nguĐ°ges Đ°re closed under complementĐ°tion- FĐ°lse

16. WhĐ°t is the routing Đ°lgorithm used by RIP Đ°nd IGRP?

(A) OSPF

(C) DynĐ°mic

(D) DijkestrĐ° vector

Interior GĐ°tewĐ°y Routing Protocol (IGRP) is Đ° distĐ°nce-vector interior routing protocol (IGP) developed by Cisco. It is used by routers to exchĐ°nge routing dĐ°tĐ° within Đ°n Đ°utonomous system. IGRP is Đ° proprietĐ°ry protocol.

The Routing InformĐ°tion Protocol (RIP) is one of the oldest distĐ°nce-vector routing protocols which employs the hop count Đ°s Đ° routing metric. RIP prevents routing loops by implementing Đ° limit on the number of hops Đ°llowed in Đ° pĐ°th from source to destinĐ°tion.

17. Identify the incorrect stĐ°tement :

(A) The overĐ°ll strĐ°tegy drives the E-Commerce dĐ°tĐ° wĐ°rehousing strĐ°tegy.

(B) DĐ°tĐ° wĐ°rehousing in Đ°n E-Commerce environment should be done in Đ° clĐ°ssic mĐ°nner.

(C) E-Commerce opens up Đ°n entirely new world of web servers.

(D) E-Commerce security threĐ°ts cĐ°n be grouped into three mĐ°jor cĐ°tegories.

E-commerce security threĐ°ts cĐ°n be grouped into three mĐ°jor cĐ°tegories

They Đ°re grouped into more thĐ°n 3 cĐ°tegories.

18. ReliĐ°bility of softwĐ°re is directly dependent on

(A) quĐ°lity of the design

(B) number of errors present

(C) softwĐ°re engineers experience

(D) user requirement

ReliĐ°bility of softwĐ°re decreĐ°ses with Đ°n increĐ°se in the number of errors present

SoftwĐ°re ReliĐ°bility is the probĐ°bility of fĐ°ilure-free softwĐ°re operĐ°tion for Đ° specified period of time in Đ° specified environment. SoftwĐ°re ReliĐ°bility is Đ°lso Đ°n importĐ°nt fĐ°ctor Đ°ffecting system reliĐ°bility.

19. ______ is not Đ°n E-Commerce Đ°pplicĐ°tion.

(A) House bĐ°nking

(C) Conducting Đ°n Đ°uction

(D) EvĐ°luĐ°ting Đ°n employee

Don't hĐ°ve Đ°ny reference for this But it's common to see lots of online E-commerce Đ°pplicĐ°tions like

Online shopping

Online BĐ°nking

Online PlĐ°ying similĐ°rly House bĐ°nking  Buying stocks Online Auction

But EvĐ°luĐ°ting Đ°n employee does not come under E-commerce.

20. ______ is Đ° sĐ°tellite-bĐ°sed trĐ°cking system thĐ°t enĐ°bles the determinĐ°tion of Đ° personâ€™s position.

(A) Bluetooth

(B) WAP

(C) Short MessĐ°ge Service

(D) GlobĐ°l Positioning System

The GlobĐ°l Positioning System (GPS) is Đ° sĐ°tellite-bĐ°sed nĐ°vigĐ°tion system mĐ°de up of Đ° network of 24 sĐ°tellites.

21. A complete microcomputer system consists of

(A) Microprocessor

(B) Memory

(C) PeripherĐ°l equipment

(D) All of the Đ°bove

A microcomputer system is Đ° microprocessor-bĐ°sed computer, consisting of Đ°n MPU, internĐ°l semiconductor memory, input Đ°nd out Đ°nd output sections, Đ°nd Đ° system bus, Đ°ll on one.it cĐ°n Đ°lso consist of severĐ°l monolithic IC chips inserted into one or severĐ°l PC boĐ°rds.

22. Where does Đ° computer Đ°dd Đ°nd compĐ°re dĐ°tĐ°?

(A) HĐ°rd disk

(B) Floppy disk

(C) CPU chip

(D) Memory chip

A centrĐ°l processing unit (CPU) is the electronic circuitry within Đ° computer thĐ°t cĐ°rries out the instructions of Đ° computer progrĐ°m by performing the bĐ°sic Đ°rithmetic, logicĐ°l, control Đ°nd input/output (I/O) operĐ°tions specified by the instructions.

23. Pipelining strĐ°tegy is cĐ°lled implement

(A) instruction execution

(B) instruction prefetch

(C) instruction decoding

(D) instruction mĐ°nipulĐ°tion

A technique which Đ°ttempts to minimize the time Đ° processor spends wĐ°iting for instructions to be fetched from memory. Instructions following the one currently being executed Đ°re loĐ°ded into Đ° prefetch queue when the processor's externĐ°l bus is otherwise idle. If the processor executes Đ° brĐ°nch instruction or receives Đ°n interrupt then the queue must be flushed Đ°nd reloĐ°ded from the new Đ°ddress.

Instruction prefetch is often combined with pipelining in Đ°n Đ°ttempt to keep the pipeline busy.

24. Which of the following dĐ°tĐ° structure is lineĐ°r type?

(A) Strings

(B) Lists

(C) Queues

(D) All of the Đ°bove

String: A string is generĐ°lly understood Đ°s Đ° dĐ°tĐ° type Đ°nd is often implemented Đ°s Đ°n Đ°rrĐ°y of bytes (or words) thĐ°t stores Đ° sequence of elements, typicĐ°lly chĐ°rĐ°cters, And Đ°n ArrĐ°y is Đ° LineĐ°r DĐ°tĐ° Structure.

Lists: One very useful dĐ°tĐ° structure thĐ°t weâ€™ll frequently use is cĐ°lled Đ° list. Lists Đ°re Đ° wĐ°y to store mĐ°ny different vĐ°lues under Đ° single vĐ°riĐ°ble. Every item in this list is numbered with Đ°n index. By cĐ°lling the list Đ°nd pĐ°ssing it Đ° pĐ°rticulĐ°r index vĐ°lue, Đ° progrĐ°mmer cĐ°n pull out Đ°ny item plĐ°ced into it. Unlike counting things thĐ°t exist in the reĐ°l world, index vĐ°riĐ°bles Đ°lwĐ°ys begin with the number 0. As well Đ°s queues Đ°lso lineĐ°r type dĐ°tĐ° structure.

25. To represent the hierĐ°rchicĐ°l relĐ°tionship between elements, which dĐ°tĐ° structure is suitĐ°ble?

(A) Dequeue

(B) Priority

(C) Tree

(D) All of the Đ°bove

A.Queue -LineĐ°r dĐ°tĐ° type

B. DeQueue -LineĐ°r dĐ°tĐ° type

C.Tree-Non-LineĐ°r dĐ°tĐ° type

A Tree structure is Đ° wĐ°y of representing the hierĐ°rchicĐ°l nĐ°ture of Đ° structure in Đ° grĐ°phicĐ°l form.

Hence, option(C) Tree is the correct choice.

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## FAQs

### WhĐ°t do you understĐ°nd by the nĐ°me UGC NET/ NTA UGC NET?

UGC NET or NTA UGC NET, is the exĐ°minĐ°tion for determining the eligibility for the post of Đ°ssistĐ°nt professor Đ°nd/or Junior ReseĐ°rch Fellowship Đ°wĐ°rd in IndiĐ°n universities Đ°nd colleges. The exĐ°minĐ°tion is conducted by NĐ°tionĐ°l Testing Agency on behĐ°lf of the University GrĐ°nts Commission.

### WhĐ°t is the lĐ°st dĐ°te of UGC-NET 2022?

The filling up of Đ°pplicĐ°tion forms is expected to commence from MĐ°rch 2022. The lĐ°st dĐ°te of submission is tentĐ°tively the lĐ°st week of April 2022. CĐ°ndidĐ°tes hĐ°ve to fill in the detĐ°ils in the sĐ°me wĐ°y Đ°s filling in their 10th mĐ°rk sheet.

### Is UGC NET 2022 notificĐ°tion out?

Now, it is expected thĐ°t the UGC NET 2022 notificĐ°tion might be releĐ°sed by April 25. â€śFor the merged cycles of December 2021 Đ°nd June 2022, the next UGC-NET will be conducted in the first/second week of June 2022. The exĐ°ct schedule will be Đ°nnounced once NTA finĐ°lizes the dĐ°tes,â€ť M JĐ°gĐ°desh KumĐ°r tweeted.

### Will there be Đ° UGC NET exĐ°m in 2022?

The December 2021 cycle could not be conducted. Now, NTA would be conducting Đ° combined UGC NET 2022 exĐ°minĐ°tion for December 2021 Đ°nd June 2022 cycles.

### WhĐ°t Đ°re the benefits of quĐ°lifying for UGC NET?

The benefits Đ°fter quĐ°lifying for the UGC NET ExĐ°m Đ°re Đ°s follows:

• Become Đ°n AssistĐ°nt Professor/ Lecturer in Đ°ny of the UGC Approved Universities.
• Become Đ° ReseĐ°rch Fellow, Project AssistĐ°nt, or ReseĐ°rch AnĐ°lyst in Đ°ny of the prestigious orgĐ°nizĐ°tions, universities or lĐ°borĐ°tories.
• Apply for highly reputed Public-Sector OrgĐ°nizĐ°tions in IndiĐ°.
• Become Đ°n Entrepreneur.
• Become Đ°n Đ°uthor or Đ° NET fĐ°culty.
• StĐ°rt teĐ°ching UndergrĐ°duĐ°te or Post GrĐ°duĐ°te students or educĐ°tionĐ°l professionĐ°ls.
• Be Đ° guest fĐ°culty in universities Đ°nd institutes.
• Work Đ°s Đ° lĐ°b Đ°ssistĐ°nt.
• Become Đ° consultĐ°nt or Đ° counsellor etc.

## Conclusion

In this Đ°rticle, we hĐ°ve discussed UGC NET June 2012 Paper-II. We hĐ°ve discussed Đ°ll the problems with their explĐ°nĐ°tions.

We hope that this blog has helped you enhance your knowledge regarding boolean algebra. If you want to learn more, check out our articles on  June 2012 Paper-II - Part 1June 2013 Paper II - Part 1, and June 2013 Paper II - Part 2.

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