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Last Updated: Mar 27, 2024
Difficulty: Easy

Secondary memory and DMA

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Introduction

Secondary memory is non-volatile, persistent computer memory that is not immediately accessible by a computer or processor. DMA is a feature of computer systems that allows specific hardware subsystems to access main system memory without the intervention of the central processor unit (CPU).

Question 1   

Cache memory with a 0.8 hit rate has a 10 ns access latency and a 100 ns miss penalty. The cache is optimized in order to lower the miss rate. However, the optimization causes a 15-ns increase in cache access latency, while the miss penalty remains the same. The minimal hit rate (rounded to two decimal places) required after optimization to keep the average memory access time from increasing is

GATE CS 2022

Answer: 0.85

Explanation: 

For a given cache, Average memory access time can be computed as:
AMAT=HitTime + Miss rate ∗ Miss Penalty

Initially,
Hit rate of cache=0.8 
∴ Miss rate=0.2
Access Latency = HitTime=10𝑛𝑠
Miss Penalty=100𝑛𝑠
AMAT𝑢𝑛𝑜𝑝𝑡𝑖𝑚𝑖𝑧𝑒𝑑=10+0.2(100)=30𝑛𝑠
For the optimized cache,
Access Latency = HitTime=15𝑛𝑠
∴AMAT𝑜𝑝𝑡𝑖𝑚𝑖𝑧𝑒𝑑=15+𝑥(100)
Now,
AMAT𝑢𝑛𝑜𝑝𝑡𝑖𝑚𝑖𝑧𝑒𝑑⩾AMAT𝑜𝑝𝑡𝑖𝑚𝑖𝑧𝑒𝑑
30⩾15+100𝑥
⟹15⩾100𝑥
⟹0.15⩾𝑥
⟹0.85⩽1−𝑥
∴The required hit rate=(1−𝑥)=0.85

Question 2

Consider a typical disk that rotates at 15000 rotations per minute (RPM) and has a transfer rate of 50 × 106 bytes/sec. If the average seek time of the disk is twice the average rotational delay and the controller’s transfer time is 10 times the disk transfer time, the average time (in milliseconds) to read or write a 512 byte sector of the disk is _____________?

GATE CS 2015 Set 2

Answer: 6.1 and 6.2

Explanation:

Seek time + rotation time + transfer time + controller  Overhead= Disc latency

Seek Time? Depends on no. tracks the arm moves and seeks the speed of the disc

Rotation Time? depending on the rotating speed and the distance between the sector and the head

Transfer Time? relies on the request size and the data rate (bandwidth) of the disc (bit density).

Seek time + rotation time + transfer time + controller overhead = disc latency

[On average, half a rotation is made] Average Rotational Time = (0.5)/(15000 / 60) = 2 milliseconds

The average seek time is indicated to be twice the average rotational delay, therefore Avg. Seek Time = 2 * 2 = 4 milliseconds.

10.24 microseconds = 512 / (50 x 10^6 bytes/sec)

Controller Overhead = 10 * 10.24 microseconds = 0.1 milliseconds Controller Overhead = 10 * 10.24 microseconds = 0.1 milliseconds

Disk latency = Seek Time + Rotation Time + Transfer Time + Controller Overhead

             = 4 + 2 + 10.24 * 10-3 + 0.1 milliseconds

             = 6.1 milliseconds

Question 3  

Consider a disc pack with a 4 millisecond seek time and 10000 revolutions per minute rotational speed (RPM). Each track comprises 600 sectors, each of which can hold 512 bytes of data. Consider a file on a hard drive. There are 2000 sectors in the file. Assume that every sector requires a seek and that the average rotational delay for accessing each sector is half that of a full rotation. The total time required to read the full file (in milliseconds) is

  1. 14000
  2. 14020
  3. 25032
  4. 14002

GATE CS 2015 Set 1

Answer: B

Explanation:

(Given) seek time = 4ms

RPM = 10000 rotations per minute (60 seconds)

As a result, a single rotation will take =60/10000 =6ms [rotation speed].

Latency of rotation = 1/2 * Latency of rotation = 1/2 *

Total time to access a file = seek time + rot. latency + transfer time. To calculate transfer time, find the transfer rate.

Transfer rate = bytes on track /rotation speed \sso, transfer rate = 600*512/6ms =51200 B/ms

transfer time= total bytes to be transferred/ transfer rate \sso, Transfer time =2000*512/51200 = 20ms

Each sector necessitates the use of seeking tim + rot. 4ms + 3ms = 7ms lag

Total time for 2000 sectors = 2000*7 milliseconds = 14000 milliseconds

Total time = 14000 + 20 (transfer time) = 14020 ms to read the entire file

Question 4   

Four files of 11050 bytes, 4990 bytes, 5170 bytes, and 12640 bytes must be saved in a computer system. We can either use 100-byte disc blocks or 200-byte disc blocks to store these files on disc (but we can't mix block sizes). 4 bytes of bookkeeping information must be kept on the disc for each block utilized to store a file. As a result, the total space used to store a file is the sum of the space used to store the file and the space used to store the bookkeeping information for the blocks used to store the file. A disc block can only store one of two things: bookkeeping information for a file or data from a file. What is the total amount of space needed to store the files using 100 and 200-byte disc blocks, respectively?

  1. 35400 and 35800
  2. 35800 and 35400
  3. 35400 and 35600
  4. 35600 and 35400

GATE IT 2005

Answer: D

Explanation:

Using disc blocks of 100 bytes:

1. A file with a size of 11050 bytes

The number of blocks needed to store data is 11050/100 = 111.

(111 * 4)/100 = 5 blocks required for bookkeeping

111 + 5 = 116 total blocks

2. A file with a size of 4990 bytes

4990/100 = 50 blocks required to store data

(50 * 4)/100 = 2 blocks required for bookkeeping

50 + 2 = 52 total blocks

3. A file with a size of 5170 bytes

Data storage blocks required = 5170/100 = 52

(52 * 4)/100 = 3 blocks required for bookkeeping

52 + 3 = 55 total blocks

4. A file with a size of 12640 bytes

The number of blocks needed to hold data is 12640/100 = 127.

(127 * 4)/100 = 6 blocks required for bookkeeping

127 + 6 = 133 total blocks

(116 + 52 + 55 + 133) * 100 = 35600 bytes total space required for storing the files using 100 byte disc blocks

Question 5   

Which of the following DMA transfer techniques and interrupt handling mechanisms will give you the most I/O bandwidth?

  1. Transparent DMA and Polling interrupts
  2. Cycle-stealing and Vectored interrupts
  3. Block transfer and Vectored interrupts
  4. Block transfer and Polling interrupts

GATE IT 2006

Answer: C

Explanation:

The block transfer instruction transfers multiword structures from one address to another or compares two multiword structures for equality.

A vectored interrupt is an I/O interrupt in a computer that informs the section of the computer that handles I/O interrupts at the hardware level that an I/O device has requested attention and also identifies the device that delivered the request.

Question 6   

The address space of the 8086 CPU is

  1. 256 Kilobytes
  2. 1 K Megabytes
  3. 64 Kilobytes
  4. one Megabyte

GATE CS 1998

Answer: D

Explanation:

The 8086's "16-bit microprocessor" identity was cemented by the fact that all internal registers, as well as internal and external data buses, are 16 bits wide. A 1 MB physical address space is provided by a 20-bit external address bus (220 = 1,048,576 x 1 byte).

Question  7  

Which of the following statements about the daisy chain scheme of linking I/O devices is correct?

  1. It provides different devices with non-uniform precedence.
  2. It gives all devices the same priority.
  3. It's only good for attaching slow devices to a CPU
  4. Each device requires its own interrupt pin on the processor.

GATE CS 1996

Answer: A

Explanation:

It is true that the daisy chain approach of linking I/O devices delivers non-uniform priority to various devices.

A daisy chain is a sequence of interconnections between computer devices, peripherals, or network nodes. It's the equivalent of a series of an electrical circuits in the computer.

Small computer system interfaces and firewire are examples of "daisy-chainable" interfaces in personal computing, which allow PCs to connect with peripheral gear such as disc drives, tape drives, CD-ROM drives, printers, and scanners.

A daisy chain is a network topology that specifies how network nodes, or computers, are connected. Various network topologies support goals such as simplicity of use, persistence, and fault tolerance.

Question 8  

A DMA controller's data count register is 16 bits in length. A file of 29,154 kilobytes must be transferred from the disc to the main memory by the processor. Byte-addressable memory is available. The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disc to the main memory is

  1. 456
  2. 3644
  3. 3649
  4. 1825

GATE CS 2016 Set 1

Answer: A

Explanation: 

The DMA controller's data count register is 16 bits in size. The maximum amount of data that may be sent in one go is 216 bytes or 64 kilobytes.

The file to be transferred has a size of 29154 kilobytes.

So, the number of times the DMA controller must obtain system bus control from the processor in order to move a file from the disc to main memory = ceil(29154/64) = 456.

Question 9   

To generate a total of 25 control signals, a micro program control unit is required. Assume that at most two control signals are active during any microinstruction. To generate the needed control signals, the minimum number of bits required in the control word will be

  1. 2.5
  2. 10
  3. 2
  4. 12

GATE CS 1996

Answer: B

Explanation: 

Because the question is about the smallest bits for control signals, we can only assume vertical microprogramming. Now, in vertical, we take a decoder, and with the assistance of the decoder, we can generate 25 signals with at least 5 bits, but we can only generate 1 signal with this, and to make 2 signals, we need another 5 bits, so we can generate any combination of 2 signals.

Must Read hardwired and microprogrammed control unit, microprogrammed control unit

Question 10   

Which of the following systems is the best choice for a pipe and filter architecture?

  1. expert system
  2. DB repository
  3. Aircraft flight controller
  4. Signal processing

GATE IT 2007

Answer: D

Explanation: 

In the pipes and filters pattern, components are filters and connectors are pipes.

Each filter takes some form of input and creates a different form of output, which may or may not be identical to the input form.

Because of the processing done inside the filter, each filter should hopefully contribute value to the output stream. Each filter is self-contained and unaffected by the upstream and downstream filters. Data streams go through pipes. UNIX shells, signal processing systems, and distributed systems are all examples of pipelines and filter architectural patterns.

Question 11   

To give a memory capacity of 16K16, how many address and data lines are required?

  1. 10,4
  2. 16,16
  3. 14,16
  4. 4,16

GATE CS 2021

Answer: C

Explanation: As we know ROM memory size = 2m x n 

=> m = no. of address lines

=> n = no. of data lines

Given, 16K × 16 = 214 × 16

=> Address lines = 14

=> Data lines = 16

Option C is the right answer

Question 12   

What is micro program ?

  1. In microcomputers, the name of a source programme.
  2. In response to a machine-language command, a set of micro instructions determines the individual operations.
  3. In assembly language programming, a basic version of macros is utilised.
  4. A short portion of machine code

GATE CS 2018

Answer: B

Explanation: A microprogram is a collection of microinstructions that describe operations in response to a machine level command.

As a result, option B is right.

Question 13   

A transfer scheme other than burst mode is used in the DMA transfer system.

  1. cycle technique
  2. stealing technique
  3. cycle stealing technique
  4. cycle bypass technique

GATE CS 2011

Answer: C

Explanation: To transmit data from input-output devices to main memory and vice versa, DMA employs a variety of transfer mechanisms. Burst Mode is a mode that allows you to make a DMA is allowed complete access to the Bus in Burst mode until the data transfer is completed. No other device, including the CPU, can access the data bus during this time. This mode allows data to be sent from memory to a device at a rapid rate. Cycle thievery is a method of stealing in which you DMA steals machine cycles from the CPU without interrupting it in cycle stealing mode. This is accomplished using a system with distinct instruction and data memory banks, which allows external devices to access data bank memory while the CPU fetches instructions from the instruction bank, ensuring that CPU utilisation is not disrupted. 

Question 14   

The width of microinstructions recorded in a processor's control memory is 26 bits. Each microinstruction has three fields: a 13-bit micro-operation field, an X field for the next address, and a MUX select field (Y). The MUX has eight status bits in its inputs. In the X, how many bits are there?

  1. 10, 3, 1024
  2. 8, 5, 256
  3. 5, 8, 2048
  4. 10, 3, 512

GATE CS 2009

Answer: A

Explanation: We need three select inputs to select and input lines because the MUX has eight states bits as input lines.
The number of bits in the control memory's next address field is 26-13-3, which equals 10 bits of addressing.
We have a total of two ten-gigabytes of memory.

So X,Y size=10,3

So (A) is correct option.

Question 15   

A computer uses ternary system instead of the traditional binary system. An n bit string in the binary system will occupy

  1. 3 + n ternary digits
  2. 2n / 3 ternary digits
  3. n(log23) ternary digits
  4. n(log32 ) ternary digits

GATE CS 2018

Answer: D

Explanation:Let 'x' be the number of digits occupied by the ternary system.
Now, Maxi. value in ternary system with x digits = Maxi. value in binary system with n digits.

3x-1=2n-1

x=log32n = n log32   (d)

Question 16  

256M X 4-bit DRAM chips are used to create a 32-bit wide main memory unit with a capacity of 1 GB. In a DRAM chip, there are 214 rows of memory cells. A single refresh process takes 50 nanoseconds to complete. The refresh rate is 2 milliseconds per second. The percentage of time available for executing memory read/write operations in the main memory unit is (rounded to the nearest integer). It should be noted that this was a Numerical Type question.

  1. 59
  2. 40
  3. 99
  4. None of these

GATE CS 2018

Answer: A

Explanation: The total number of rows is 214, and it takes 50 nanoseconds to conduct one refresh operation.
As a result, the total time required to conduct the refresh operation is214*50 nanoseconds = 819200 nanoseconds = 0.819200 milliseconds.
However, the refresh time is 2 milliseconds.
As a result, the percentage of time spent in the refresh period is (0.819200 milliseconds) / (2 milliseconds) = 0.4096 = 40.96 percent.
As a result, the time spent in read/write operations is equal to 100 percent – 40.96 percent = 59.04 percent = 59.04 percent (in percentage and rounded to the closest integer).
As a result, the correct answer is 59.

Question 17   

How many address lines are required to access RAM chips placed in a 4 x 6 array, each chip being 8K x 4 bits, if each address space represents one byte of storage capacity?

  1. 13
  2. 15
  3. 16
  4. 17

GATE CS 2014

Answer: D

Explanation: Size of each Ram chip = 8K x 4 bits = 23 x 210  x 22 

=215  bits = 212  bytes

Number of chips required = 6 x 4 = 24 = 5 bits

So, total number of bits required = 12 + 5 = 17 bits

Question 18   

Which of the statements about synchronous and asynchronous I/O is false?

  1. In synchronous I/O, but not in asynchronous I/O, an ISR is triggered when I/O is completed.
  2. Following the completion of both synchronous and asynchronous I/O, an ISR (Interrupt Service Routine) is called.
  3. A process that makes a synchronous I/O call waits until the I/O is complete, whereas a process that makes an asynchronous I/O call does not.
  4. The ISR that is executed after the completion of synchronous I/O wakes up the process waiting for the completion of I/O.

GATE CS 2009

Answer: B

Explanation: In synchronous I/O process performing I/O operation will be placed in blocked state till the I/O operation is completed. An ISR will be invoked after the completion of I/O operation and it will place process from block state to ready state.

In asynchronous I/O, Handler function will be registered while performing the I/O operation. The process will not be placed in the block state and process continues to execute the remaining instructions. when the I/O operation completed signal mechanism is used to notify the process that data is available.

Question 19   

In comparison to static RAM memory, dynamic RAM memory provides the following advantages:

  1. lower bit density and higher power consumption
  2. higher bit density and higher power consumption
  3. lower bit density and lower power consumption
  4. higher bit density and lower power consumption

GATE CS 2007

Answer: B

Explanation: Because there are six transistors in total (occupying more space), static RAM has a lower density than DRAM, which only has one transistor and a capacitor.

Therefore the Density (SRAM) < Density of (DRAM).

Question 20   

In a computer with two physical quad-core chips and hyper threading enabled, the number of logical CPUs is

  1. 1
  2. 2
  3. 8
  4. 16

GATE CS 2014

Answer: D

Explanation: In hyperthreading, each physical CPU equates to two logical CPUs, and there are two quad core devices.

As a result, the total number of physical CPUs is equal to 2*4 = 8.

8 physical CPUs now equal 2*8 = 16 logical CPUs.

A multi-core processor is a single piece of hardware ("one processor") with multiple cores that can work at the same time.

You can also read about the memory hierarchy.

FAQs

What are the questions asked in GATE?


There are two sorts of MCQs: MCQs: 1 point for each valid answer; 1/3 point subtracted for each incorrect answer. MCQs: 2 marks for each correct response; 2/3 marks will be deducted for each incorrect response. Numerical Answer Type (NAT) questions have no negative indications.

Are there any restrictions or age limits to applying for the GATE Exams 2023?


No, there are no restrictions on the number of times. 

What are the GATE Exam eligibility requirements?


The candidate should have done their Bachelors in Science or Engineering.

Is PSU recruitment through GATE beneficial?


Yes, those who want to work in the government after finishing their engineering degree should take the GATE exam and then apply for PSU jobs.

What is GATE?


The Graduate Aptitude Test in Engineering (GATE) is a pan-India examination organized by the Indian Institute of Science (IISc) in Bangalore and the seven Indian Institutes of Technology (IITs).

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Conclusion

To summarize the above blog we have solved the previous year's GATE Questions. Attempt these questions on your own and only refer to the Explanation when required and you are not able to solve the question on your own.

Hope you learned something. But the knowledge never stops.

If you want to learn more, check out our articles on Introduction to GATEHow to prepare in the Last 10 days to score high in GATE?

Recommended Readings:

Refer to our guided paths on Coding Ninjas Studio to learn more about DSA, Competitive Programming, JavaScript, System Design, etc. 

Enroll in our courses and refer to the mock test and problems available.

Take a look at the interview experiences and interview bundle for placement preparations.

Happy Learning Ninja :) 

Topics covered
1.
Introduction
2.
FAQs
2.1.
What are the questions asked in GATE?
2.2.
Are there any restrictions or age limits to applying for the GATE Exams 2023?
2.3.
What are the GATE Exam eligibility requirements?
2.4.
Is PSU recruitment through GATE beneficial?
2.5.
What is GATE?
3.
Conclusion