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Table of contents
1.
Introduction
1.1.
 Instructions
2.
Addressing Modes
3.
Example
4.
Program and Instruction cost
5.
Frequently Asked Questions
5.1.
What is a Target Machine?
5.2.
What is the cost of MOV R0, and R1?
5.3.
What are the host machine and target machine?
5.4.
What is the target language in compiler design?
5.5.
What role does the target machine play in the compiler's code generation?
6.
Conclusion
Last Updated: Mar 27, 2024

Target Machine

Author yuvatimankar
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Compiler Design

Introduction

A target machine is a byte-addressable machine with 4 bytes for a word. The target machine has a general-purpose register R0, R1….Rn-1. 

The target machine also has three address instructions: op, source, and destination, where op is used as an op-code, and source and destination are used as a data field.

The target machine has the following op-code: 

ADD(it adds source to destination)

SUB(it subtracts source from destination)

MOV(it moves source to destination)

A target machine is related to the last phase of the compiler, i.e., the code generator. A code generator is a machine-dependent phase of the compiler because whatever the input is given to the code generator, the code generator converts the input into the final target code.

Also see, Phases of Compiler and,Lexical Analysis in Compiler Design

 Instructions

 Instructions available in the target machine are as follows:

  • Store operation: ST r, x; this instruction stores the value in location x to register r.
  • Load operation: LD dst, addr this instruction loads addr location value into location dst. It means dst=addr. This instruction will load the value of location x to location r.
  • Conditional jump: The standard form of this operation is Bond,r, L. Where r is registered, L is a label, and cond stands for any of the general tests on the value in register r.
  • Unconditional jump: BR L; this operation jumps from branch BR to level L.
  • Computation operations: OP dst, src1, src2 OP like operator ADD, SUB.

Addressing Modes

  • Variable name: X i.e LD r1,X
  • Indexed address: a(r) like LD R!,a(R2) this instruction means R1= contents(a+contents(R2))
  • Integer indexed by a register: LD R1, 100(R2)
  • Indirect addressing mode: *r and *100(r)
  • Immediate constant addressing mode: LD R1, #100

Also See, Top Down Parsing

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Example

LD R0, R1: This instruction loads the contents of register R1 into register R0. The cost of this instruction is one because no memory is required to perform this operation.

LD R1, *100(R2): This instruction will load the value given by contents(contents(100 + contents (R2)) into register R1. The cost of this instruction is two because the constant 100 is stored in the word by following the instruction.

MOV R0, M: This instruction moves register R0 to memory location M . Cost of this instruction is three since the address of memory location M is in the word following the instruction.

Convert the following address code into target code:

  1. b = a[i]

Step1: LD R1, i   // Load the value of i to R1

Step2: MUL R1, R1,8 

 // R1= R1*8 because we have considered the array as a float.

Step3: LD R2, a(R1)   // Load a(R1) to R2

Step4: ST b, R2      // store R2 to b

2. a[j] = c

Step1: LD R1,c   //Load c to R1

Step2: LD R2,j    // Load j to R2

Step3: MUL R2, R2,8  //Because of float we will multiply by 8

Step4: ST a(R2), R1    // Store R1 to R2

Program and Instruction cost

  • If we want to select an instruction, we will select an instruction whose programming costs are less. every machine will have its fixed instruction cost.
  • In most of the machines and in most of the instructions the time taken to fetch an instruction from memory exceeds the time spent executing the instruction, so if the length of the instruction is reduced it has an extra benefit.
Instruction operation cost
MOV R0, R1 (Register to register) 1
MOV R0, M (Register to memory) 2
MOV M, R0(Memory to register) 2
MOV 4(R0), M (4+contents(R0) into memory) 3
MOV *4(R0,M) contents(contents(4+contents(R0))) into memory 3
MOV #1, R0  (store 1 into R0) 3
ADD 4(R0),*12(R1)  (add contents(4+contents(R0) to value at location contents(12+ contents(R1)) 3

Frequently Asked Questions

What is a Target Machine?

A target machine is a type of byte-addressable machine. It has two address instructions: op source and destination.

What is the cost of MOV R0, and R1?

This instruction copies the content of register R0 into R1. The cost of this instruction is one as it occupies only one word of memory.

What are the host machine and target machine?

The host machine is nothing but the machine that you are building for, and the machine that GCC will produce code for is called target machine.

What is the target language in compiler design?

Compiler design uses assembly language to convert optimized code into the machine-understandable format.

What role does the target machine play in the compiler's code generation?

A major role that target machines play in code generation is to deploy more sophisticated instructions, which can have the capability to perform certain instructions much more efficiently.

Conclusion

In this article, we have extensively discussed the target machine and some of its examples in detail. 

After reading about the target machines, are you not feeling excited to read/explore more articles on the topic of compiler design? Don’t worry, Coding Ninjas has you covered. To learn, see the compiler design course, and you can visit our website coding ninjas!  

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