VLSI Interview Questions and Amswers

Introduction

VLSI (Very Large-Scale Integration) involves packing hundreds of thousands of transistors onto a single silicon chip. It's a key technology for microchips, integrated circuits (ICs), and component design, widely adopted by companies worldwide. 

With more and more companies shifting towards VLSI, one must be well prepared with the VLSI interview questions to get a job in the field. In this blog, we will discuss the most asked VLSI interview questions.

 

Top 30 Most Asked VLSI Interview Questions 

Now, let us look at some of the most asked VLSI interview questions to crack your interviews.

1. Explain the procedural blocks in Verilog.

Ans: A procedural block in a Verilog is a group of statements executed whenever a change in the sensitivity list signal calls the block.

Procedural blocks are of two types: 

1. Initial blocks: Initial block is only executed once at zero
2. Always blocks: On the other hand, Always blocks are executed recursively in a loop.

2. Explain the different types of ports used in Verilog.

Ans: There are three different types of ports used in Verilog:

1. Output port output: With the output port, the module can only direct values from output ports.
2. Bidirectional port inout: With the help of inout ports, the module can both send and receive data from outside.
3. Input port input: With the input port, the module accepts data from outside from input ports.

3. Define FGPA.

Ans: FGPA stands for Field Programmable Gate Array. It is an integrated circuit composed of internal logic blocks (greater than 20,000 gates) that have programmable interconnects and performs the user logic, which is the code provided by the user. FGPAs are useful in parallel computing, which increases their performance as compared to the standard CPUs. The programs on the multipurpose chip can be modified as many times for different applications. Verilog programming languages are used to write the code in FGPA.

4. Explain setup time.

Ans: Setup time is the minimum time required for an input signal to achieve stability before the clock's sampling event. Setup time helps recognize the correct input signal.

5. What role does boolean logic play in controlling the logical gates?

Ans: In boolean logic, the false state is represented by 0, whereas the true state is represented by 1. The logic high denotes the presence of potential in digital electronics. 

6. Define slack in VLSI.

Ans: Slack is defined as the difference between a signal's desired and actual time. It decides whether the design is operating at a preferred frequency. Positive slack indicates that the design is working within the time limits, but improvisation can be made. Zero slack means that the design is working at the preferred frequency.

7. Name the relevant logic gates where Boolean logic operates.

Ans: Boolean logic operates on OR Gate, AND Gate, NOT Gate, NAND Gate, NOR Gate, XOR Gate, and XNOR Gate.

OR Gate: When either of the input is high, the output will always be high in an OR gate. The output is always low when both inputs are low.

AND Gate: When either of the input is low, the output will always be low in an OR gate. The result is always high when both inputs are high.

NOT Gate: In NOT gate, the output is always reversed to that of the input. If the input is high, the output will be low, and vice versa.

NAND, NOR XOR, and XNOR gates are built with the combination of the above basic logic gates.

8. What is the use of a multiplexer?

Ans: A Multiplexer is a device that selects multiple digital and analog input signals and redirects the inputs into a single output stream. With the help of a multiplexer, the cost of communication is reduced, and efficiency is enhanced. Multiplexing is of three types:

• Frequency Division Multiplexing
• Time Division Multiplexing, and
• Wavelength Division Multiplexing

9. How does Verilog differ from other programming languages?

Ans: Verilog is a Hardware Descriptive Language that engineers use for designing in VLSI platforms like FGPA and ASIC. In contrast, programming languages like C, C++, and java are software languages representing successive operations.

10. What is threshold voltage?

Ans: The minimum voltage between the gate and source terminal that results in the formation of an inversion layer connecting the source and drain is known as the threshold voltage of MOSFET. This voltage defines the working of MOSFET. If the minimum voltage exceeds the threshold voltage, then MOSFET will remain in the cut-off region.  

11. Differentiate between CMOS and TTL chips.

Ans:

CMOS chips	TTL chips
Complementary Metal Oxide Semi-conductor uses field effect transistor.	Transistor Transistor Logic, or TTL, uses bipolar junction transistors.
There is a higher density of logic gates in CMOS.	The density of TTL is comparatively less.
Work at a faster speed	TTL chips operate slower than CMOS
CMOS chips use less power. One single CMOS chip utilizes 10nW of power.	TTL chips consume more energy. A single gate in TTL consumes mW of energy.
CMOS chips are used in mobile	TTL chips come into application in computers

12. How can you stop metastability in VLSI?

Ans: Metastability occurs when a clock signal and a data signal are nonparallel. Metastability can be avoided by double-flopping the data. 

13. Define SCR.

Ans: SCR, or Silicon Control Rectifier, is a silicon thyristor that converts AC voltage to DC voltage. The 4-layer diode controls high power and switches between on and off states through gate input controls.

14. Mention some advantages of MOSFETs over BJTs.

Ans: Some advantages of MOSFETs over BJTs are:-

• MOSFETs are very small compared to BJTs. This helps the MOSFETs cover a tiny silicon area in the integrated circuit. 
• The packing density of MOSFETs is high.
• MOSFETs consume less energy as compared to BJTs.
• MOSFET is a 4-terminal device, whereas BJTs is a 3-terminal device.
• MOSFETs are simpler to manufacture when compared to BJTs.
• MOSFETs are unipolar devices that control voltage. BJTs are Polar devices used to direct current.

15. Briefly explain the purpose of tie cells.

Ans: Tie cells are used to provide constant high and constant low voltage. Tie cells prevent the transistors from damaging due to thinning of the gate oxide. Tie cells are used for inputs of the gate and unused inputs. Tie cells are of two types:

1. Tie Hi to produce constant high outputs
2. And Tie low to produce consistent low outputs.

16. How can you adjust the simulation time in Verilog?

Ans: Simulation time is the time managed by the simulator to record the actual time the circuit takes to simulate. Simulation time in Verilog can be customized using the timescale compiler directive.

17. Explain the meaning of "the channel is pinched off."

Ans: For a MOSFET, the channel is induced when the voltage between the source and gate (VGS) is greater than the threshold voltage Vt. As we increase VDS current stats flowing from drain to source, until the voltage between gate and channel at the drain end becomes Vt, i.e., VGS-VDS=Vt, the channel depth at the drain end decreases to almost zero. At this stage, the channel is said to be "pinched off." In this condition, the MOSFET enters the saturation region. 

18. On what factors does threshold voltage depend?

Ans: Threshold voltage depends on the following factors:

• Doping at Gate: As the doping at the gate rises, threshold voltage decreases.
• Substrate doping: Threshold voltage increases with substrate doping.
• The thickness of gate oxide: Thicker the gate oxide, the greater will be the threshold voltage.
• Channel length: The threshold voltage decreases with a decrease in channel length.

19. What is the number of transistors used by a static RAM?

Ans: Static RAM makes use of 6 transistors. Four transistors for cross-coupled inverters and two access transistors.

20. Compare Combinational circuits and Sequential circuits.

Ans:

Combinational Circuits	Sequential Circuits
Combinational Circuits depend on the present input to generate an output.	The output in Sequential Circuits depends on the previous and present input.
Combinational circuits are time-independent circuits.	Sequential circuits are dependent on time.
It is easy to design and operates faster.	It is challenging to design and is also comparatively slower.
Combinational circuits are used in arithmetic and boolean operations.	Sequential circuits are used in flip-flops.
Clocks are absent in combinational circuits, and hence triggering is not required.	Since clocks are present in sequential circuits, triggering is required.

21. Explain “timescale 1ns/1ps” in Verilog code.

Ans: The above line of code states that,

Unit of time = 1ns

Accuracy/precision (time_precision) = 1ps 

22. List the types of skews used in VLSIs.

Ans: Skews in VLSI can be classified into local, global, and useful skews.

1. Local skews: Local skew deals with the difference between the launching and the destination flip-flops. The variance helps in defining the time path between the two.
2. Global skews: The time gap between the earliest component appearing at the flip-flop and the latest within the same domain is defined by global skews.
3. Useful skews: The time lag in capturing the flip-flop paths is defined by useful skews. This can afterward be used to set up the environment with precise conditions for the launch and capture the timing path. The holding conditions must be met here.

23. Briefly explain MTBF in VLSI.

Ans: MTBF stands for Mean Time Between Failure. It provides the frequency of a particular element's failure and the time until a system fails.

24. What is the use of Defparam in Verilog?

Ans: Defparam is the keyword used to override the parameter values. It changes the value of the parameter at compilation time only.

25. Why are the number of gate inputs to CMOS restricted to 4?

Ans: As the number of stacks increases, the speed of the gate becomes slower. Usually, 

Number of gates in the stack of NOR = Number gates in the stack of NAND + 1

So, the inputs are restricted to 4 in number.

26. Describe the three regions of operation of a MOSFET.

Ans: The three regions of operation of MOSFET are

1. Cut-off region: When VGS<Vt, no channel is induced, and hence no current flows, then the MOSFET region will be in the cut-off region.
2. Triode region: VGS>=Vt, Channel is induced, and there is a flow of current when VDS>0.
3. Saturation region: When VGS>=Vt and VDS >=VGS-Vt, the channel will be in saturation mode.

27. What is channel length modulation?

Ans: On increasing the VDS, the channel pinch-off starts moving toward the source and away from the drain. This results in a decrease in the effective channel length. This process is called channel length modulation.

28. Differentiate between Verilog and VHDL.

Ans: 

Verilog	VHDL
It is a description language	It is a hardware modeling language
It is a case-sensitive language	It is a case-insensitive language
It supports compiler directives	It does not support compiler directives
Verilog supports transistor-level modeling	VHDL supports switch-level modeling
It is simple to code in Verilog	VHDL is more complex

29. Compare the “==” and “===” operators.

Ans: "==" checks for logical equality that is for 1 and 0, others result in x, whereas "===" checks for the logical equality of 4-states, that is 1,0,z, and x

Also, Read - Demultiplexer