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ASIC RTL Design Engineer - 3 -8 Yrs - Noida

Macropace Technologies hiring for CMMi Level 5 client
3 - 7 yrs
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Not Disclosed by Recruiter Posted 26 days ago Job Applicants: 20 Job Views: 165

Job Description

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    Requirements and specifications, micro-architectural definition for optimal area and power
    Digital design RTL and verification
    Synthesis, static timing analysis, formal verification, gate-level simulations, and power estimation and optimization.
    Project deliverables may include specification documents, micro-architectural definitions, RTL code Verilog and/or System Verilog, simulation models, test benches, gate-level netlists, timing constraints, UPF files, and associated documentation and additional collateral.

Salary: Not Disclosed by Recruiter

Industry: Semiconductors / Electronics

Functional Area: Engineering Design , R&D

Role Category:Engineering Design

Role:Design Engineer

Employment Type: Permanent Job, Full Time


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Macropace Technologies

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