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ASIC Verification Engineer

3 - 5 yrs
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Not Disclosed by Recruiter Openings: 1 Posted 8 days ago Job Applicants: 19 Job Views: 288

Job Description

 
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    Minimum 6 years of relevant experience.

    4 years of experience in System Verilog HVL.

    Must have 3 year of experience in either OVM OR UVM / VMM.

    Hands on experience of developing assertion , checkers , coverage and scenario creation.

    Must have executed at - least 2 SoC Verification project

    Experience in developing test and coverage plan , Verification environment and validation plan.

    Knowledge of atleast one industry standard protocols like Ethernet , PCIe , MIPI , USB or similar is required.

Salary: Not Disclosed by Recruiter

Industry: Recruitment, Staffing

Functional Area: IT Software - Embedded , EDA , VLSI , ASIC , Chip Design

Role Category:Programming & Design

Role:Team Lead/Technical Lead

Employment Type: Permanent Job, Full Time

Keyskills

Education-

UG: B.Tech/B.E. - Computers

PG:M.Tech - Computers

Company Profile:

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Finding the right talent is one of the key issues businesses are addressing today. Talent Acquisition is no more simply a part of a generalists’ to-do list but a specialists’ forte. With over a decade and a half in contingency search across various verticals, industries and hierarchies; we are now a trusted partner to various Leading Global multinationals, both products and services, and boast of an excellent track record of delivering top notch talent across the board. We are highly rated by each client we work with. Successfully delivered several CTO's, Competency / Practice Heads and Heads of R&D to top global product brands apart from some key senior strategic hires in the Sales & Finance COE's and as diverse as Taxation to Aviation & Defence. Strongly skill agnostic.
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