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DFT Senior Engineer

9 - 14 yrs
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Not Disclosed by Recruiter Openings: 1 Posted 30+ days ago Job Applicants: Less than 10 Job Views: 171

Job Description

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    Responsible for DFT implementation including JTAG, MBIST and SCAN, Boundary SCAN.
    * Generate DFT related timing constraints and work with PD team for timing closure
    * Generate and verify DFT structural patterns and functional patterns
    * Design and implement other DFX (debug, characterization, yield etc) logics
    * Interfacing with the design teams to ensure DFT design rules and guidelines are met
    * The person should have experience in timing concepts.
    * Generating high quality manufacturing test patterns for stuck-at, transition fault models and through the use of on-chip test compression techniques
    * Simulating and verifying the ATPG and LBIST patterns
    * Working with the product engineering teams on the delivery of manufacturing test pattern
    * Developing, enhancing and maintaining scripts as necessary
    * DFT design VC_LINT and CDC violation analysis, Spyglass check;
    * Synthesize and Pre-physical netlist LEC check.

Salary: Not Disclosed by Recruiter

Industry: Semiconductors, Electronics

Functional Area: IT Hardware , Technical Support , Telecom Engineering

Role Category:IT Hardware

Role:Hardware Design Engineer

Employment Type: Full Time, Permanent




UG: Any Graduate - Any Specialization

PG:Any Postgraduate - Any Specialization

Doctorate:Doctorate Not Required

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