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Design Verification Engineer with 6- Years of Experience at Hyderabad

6 - 8 yrs
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10,00,000 - 20,00,000 PA. Openings: 3 Posted 30+ days ago Job Applicants: Less than 10 Job Views: 144

Job Description

 
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    *Experience with SV+UVM/OVM/VMM or Specman/eRM/UVMe
    *System Verilog - Language like C, UVM - methodology
    *SOC - System on Chip Verification; lot of IP's (100 ....)Proficient on protocols - AXI, AHB, USB, PCIe, DDR, LPDDR, HDMI, MIPI, Ethernet.

Salary: INR 10,00,000 - 20,00,000 PA.

Industry: Semiconductors, Electronics

Functional Area: Engineering Design , R&D

Role Category:Engineering Design

Role:Senior Design Engineer

Employment Type: Full Time, Permanent

Keyskills

uvm and sv design & verification engineer
Company Profile:

VISIONYLE SOLUTIONS PRIVATE LIMITED

Visionyle Solution Pvt Ltd, offer Services Application Development, Product Development, Consultancy Services, Digital Marketing, Business Intelligence and Analytics, Cloud Computing, and Outsourcing. Founded by some of the most intellectual
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Manager Hiring Visionyle Solutions Pvt Ltd Vijayawada

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