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HCL Technologies Hiring DFT Engineers For VLSI R and D Division

5 - 10 yrs
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Not Disclosed by Recruiter Openings: 1 Posted 30+ days ago Job Applicants: 146 Job Views: 1417

Job Description

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    Greetings from HCL Technologies !!

    HCLs VLSI Team has strong legacy of more than 23 years in the VLSI industry along with a rich experience of having worked with top chip manufacturers and design foundries across the globe. Team has the potential to develop high-end complex chip designs from concept to production-ready wafer/chip, and so far have done 200+ SOC Tape-outs (7nm, 10nm, 14nm, 28nm, 40 nm, 65nm, 90nm, 130nm, 180nm (HPM, G, GP, LP, LV, LVOD), up to 600 mm2 die size and Gate count up to 65 Million). Recently we taped out a complex System on chip (SoC) high-end derivative chip (14 nm, 28 CPU cores, 2.5 GHZ, 600mm2 die area).

    Our DFT Capability:
    - DFT architecture & Test Specification
    - Implementation (Scan, ATPG, MBIST, BSCAN, High speed interface etc.)
    - Writing test constraints, signing off test mode timing
    - Verification at various stages, Timing Simulations
    - Patten generation & tester debug
    - Production ramp-up
    - Failure analysis, Yield improvement

    HCL R&D division is hiring for the position of DFT Engineers .

    Experience: 5 to 10 yrs
    Work location: Bangalore/Chennai

    Skill Set:

    - Understand DFT architecture of IPs/SoCs
    - Integrating DFT logic at SoC level
    - Hands on experience with various DFX/DFT functionalities at IP and SoC level
    - Exposure to various sanity checks
    - Build & release to various teams
    - Interface with PD, Validation & Emulation teams
    - 5 to 10 years of hands on experience with different DFX architectures

    Hands on experience with

    - ATPG, Understanding/exposure to MBIST, JTAG
    - Coverage analysis and improvement for stuck-at, transition fault
    - various manufacturing tests (such as voltage droop, voltage monitor, die variation monitors)
    - Experience in debugging simulation failures
    - Scripting experience

    If interested, kindly revert with your profile to with below MANDATORY details. Also, share any references as we are having multiple positions for the same.

    Total experience:
    Relevant experience in DFT:
    Contact number:
    Current CTC:
    Expected CTC:
    Current company:
    Notice period:

    Arun Vikram M
    Human Resource Executive-TAG
    ERS (Engineering and R&D Services)

Salary: Not Disclosed by Recruiter

Industry: Semiconductors, Electronics

Functional Area: Engineering Design , R&D

Role Category:Engineering Design

Role:Design Engineer

Employment Type: Full Time, Permanent



UG: Any Graduate - Any Specialization

PG:Any Postgraduate - Any Specialization

Doctorate:Doctorate Not Required

Company Profile:

HCL Technologies Limited

HCL Technologies Limited
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Arun Vikram Company Recruiter HCL Technologies Limited Chennai

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