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Physical Design Engineer - 2 to 10 Yrs - Hyd/noida

Macropace Technologies hiring for CMMI Level 5 Client
2 - 7 yrs
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Not Disclosed by Recruiter Posted 19 days ago Job Applicants: 88 Job Views: 431

Job Description

 
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    Engineer would be responsible for doing Physical Design implementation, Timing Closure and Physical Verification at Block Level.
    Expertise in 7nm/14nm/16nm/28nm
    Should execute block level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks, IR Drop, STA, Power and noise analysis

Salary: Not Disclosed by Recruiter

Industry: Semiconductors / Electronics

Functional Area: Engineering Design , R&D

Role Category:Engineering Design

Role:Design Engineer

Employment Type: Permanent Job, Full Time

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Macropace Technologies

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