Roles and responsibilities
1.Expertise on Partitioning, IO ring preparation, Floor planning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis.
2. Physical verification, Signal Integrity, Low Power design Skills required Should have experience on Physical Design Implementation with sub-micron technology of 28 nm and lower technology nodes.
3. Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency Must have worked on experience with Cadence/Synopsys suite (Innovus, SOC Encounter, IC Compiler).
4. Strong experience on Static Timing Analysis (Prime Time), EM/IR-Drop/Cross-talk analysis (PT-SI, Red hawk), formal or Physical Verification (Formality, Calibre)
5. Experience in complex SOC integration, Low Power and High Speed Design and Advanced Physical Verification Techniques.
6. Provide technical guidance, mentoring to physical design engineers Interface with front-end ASIC teams to resolve issues.
Salary: Not Disclosed by Recruiter
/ Software Services
Functional Area: IT Software - Embedded
, Chip Design
Role Category: Programming & Design
Role: Team Lead/Technical Lead
Employment Type: Permanent Job, Full Time