Job Description :
JD for Physical Design:
Experience: 2-10+ years
Notice Period :- Max 45 days
Positions :- 18
Candidate will be responsible for executing the block level place and route assignments from Netlist through GDS flow.
The candidate will own the complete Physical Design including Floor Planning, Power Planning, Place and Route, CTS, Timing Closure, IR Drop Analysis, Physical Verification and Equivalence Checking.
Good understanding of timing, clock tree, routing, and DRC/LVS issues/solutions in complex ASIC designs is required.
Ability to plan and work independently and co-ordinate with cross-functional teams is essential.
Prior experience with 28nm or lower technology nodes is desired.
An expertise in physical verification is desired. The job would require scripting in TCL.
Technologies Tools: -
Netlist to GDSII / PD / Implementation flow / PnR / APR
RTL to GDSII (Synthesis and PD experience)
Low power design experience
ASIC/VLSI flow knowledge.
Floor planning, Power planning, Placement, CTS, Routing, Extraction, DFM
Congestion and timing analysis.
Sign off flow, technology node
Desired Candidate Profile
Please refer to the Job description above
UG: Any Graduate - Any Specialization
PG:Any Postgraduate - Any Specialization
Doctorate:Doctorate Not Required
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