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Physical Design Engineer

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Not Disclosed by Recruiter Posted 30+ days ago Job Applicants: 25 Job Views: 241

Job Description

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    Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs.
    Schematic (LVS) checks, Antenna checks.
    Should have worked on 45nm or lower node designs with adv. low power techniques such as Voltage Islands, Power Gating and substrate-bias

Salary: Not Disclosed by Recruiter

Industry: IT-Software, Software Services

Functional Area: IT Software - Embedded , EDA , VLSI , ASIC , Chip Design

Role Category:Programming & Design

Role:Database Architect/Designer

Employment Type: Permanent Job, Full Time


Desired Candidate Profile

    Required Skills:

    Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure
    Extensive experience and detailed knowledge in Cadence or Synopsys physical Design Tools.
    Expertise in scripting languages such as PERL, TCL
    Strong Physical Verification skill set.
    Static Timing Analysis in Primetime or Primetime-SI

    Desired Skills:

    Provide technical guidance, mentoring to physical design engineers
    Interface with front-end ASIC teams to resolve issues
    Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques
    Excellent communication skills
    Timing closure on DDR2/ DDR3/ PCIE interfaces.

    Qualification Bachelors or Masters Degree in Electronics or VLSI with relevant expertise


UG: B.Tech/B.E. - Electronics/Telecommunication

PG:M.Tech - Electronics/Telecommunication, MS/M.Sc(Science) - Electronics

Doctorate:Doctorate Not Required

Company Profile:


Product development & solutions company with determined focus to make human lives much simpler by collaborating technologies like Robotics, AI & ML.
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