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Physical Design Manager

10 - 15 yrs
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Not Disclosed by Recruiter Posted 6 days ago Job Applicants: Less than 10 Job Views: 84

Job Description

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    Job Description:

    All aspects of Physical Design including Floor Planning, Power Plan, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout.
    Should be able to manage schedules, mentor the juniors and support cross-functional engineering effort to drive to signoff closure for tapeout
    Improve design flows to meet the QoR targets and ensure predictability
    Exposure to the latest design rules, processes and innovations need to close PPA on the advance nodes.
    Manage a design team of 30-40 engineers working on all aspects of physical design

Salary: Not Disclosed by Recruiter

Industry: IT-Software / Software Services

Functional Area: IT Software - Embedded , EDA , VLSI , ASIC , Chip Design

Role Category:Project Management

Role:Project Manager-IT/Software

Employment Type: Permanent Job, Full Time


Desired Candidate Profile

    Desired Skills and Experience:

    B. Tech. / M. Tech. with 10-15 years of experience in Physical Design
    The candidate should be able to work with and lead a team of engineers on all aspects of Physical Design tasks on an SOC design
    Must have prior experience of managing a design team
    Should have handled RTL to GDS II at Chip level for multiple tape outs
    Hands-on expertise with technology nodes like 28nm, 16nm and below
    Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with ICCII & Calibre
    Along with partitioning & budgeting candidate should have hands-on experience in Chip/partition floor planning, placement optimizations, bus planning, Clock planning and routing.
    Good understanding and hands on experience with physical verification (DRC/LVS/ERC/antenna) and other reliability checks(IR/EM/Xtalk)
    Good understanding of low power implementation techniques and static low power checks
    Hands-on experience in Full chip level signoff STA
    Being proficient in TCL, Perl scripting is a plus


UG: B.Tech/B.E. - Any Specialization

PG:M.Tech - Any Specialization

Doctorate:Doctorate Not Required

Company Profile:

Invecas technologies Pvt Ltd

Invecas technologies Pvt Ltd
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