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Senior Physical Design Engineer

7 - 12 yrs
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Not Disclosed by Recruiter Openings: 1 Posted 30+ days ago Job Applicants: Less than 10 Job Views: 94

Job Description

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    with strong expertise in the area of chip/ partition floor- planning, design partition creation, budgeting and feedthrough planning

    Work alongside RTL/ Synthesis/ DFT teams to define design partitions and create floorplan as per the design data flow

    Work closely with library, technology and Analog IP teams for physical design requirements

    Work closely with CAD teams and involve in methodology development and improvement

    Own SoC/ partition physical design activities while managing a team of 4- 5 engineers Desired Skills and Experience:

    Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)

    Tech. / M. Tech. with 5- 12 years of experience in Physical Design

    The candidate should be able to work with and lead a team of engineers on all aspects of Physical Design tasks on an SOC design

    Should have handled Netlist to GDS II implementation at Chip/ partition level for atleast 2- 3 designs

    Hands- on expertise with technology nodes like 28nm, 16nm and below

    Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with ICCII & Calibre

    Excellent understanding of design partitioning & budgeting along with hands- on experience in Chip/ partition floor planning, placement optimizations, Clock planning and routing.

    Good understanding of low power implementation techniques and static low power checks

    IO ring design and bump planning is a plus

    Being proficient in TCL, Perl scripting is a plus Job Features Job Category Physical Design Apply Online A valid email address is required. United States United Kingdom Albania (Shqip ri) American Samoa Antigua and Barbuda Austria ( sterreich) Azerbaijan (Az rbaycan) Belgium (Belgi ) Benin (B nin) Bosnia and Herzegovina ( ) Brazil (Brasil) British Indian Ocean Territory British Virgin Islands Burkina Faso Burundi (Uburundi) Cameroon (Cameroun) Cape Verde (Kabu Verdi) Caribbean Netherlands Cayman Islands Central African Republic (R publique centrafricaine) Chad (Tchad) Christmas Island Cocos (Keeling) Islands Congo (DRC) (Jamhuri ya Kidemokrasia ya Kongo) Congo (Republic) (Congo- Brazzaville) Cook Islands Costa Rica C te d Ivoire Croatia (Hrvatska) Cura ao Czech Republic ( esk republika) Denmark (Danmark) Dominican Republic (Rep blica Dominicana) El Salvador Equatorial Guinea (Guinea Ecuatorial) Estonia (Eesti) Falkland Islands (Islas Malvinas) Faroe Islands (F royar) Finland (Suomi) French Guiana (Guyane fran aise) French Polynesia (Polyn sie fran aise) Germany (Deutschland) Ghana (Gaana) Greenland (Kalaallit Nunaat) Guinea (Guin e) Guinea- Bissau (Guin Bissau) Hong Kong ( ) Hungary (Magyarorsz g) Iceland ( sland) Isle of Man Italy (Italia) Latvia (Latvija) Lithuania (Lietuva) Macedonia (FYROM) ( ) Madagascar (Madagasikara) Marshall Islands Mauritius (Moris) Mexico (M xico) Moldova (Republica Moldova) Montenegro (Crna Gora) Mozambique (Mo ambique) Myanmar (Burma) ( ) Namibia (Namibi ) Netherlands (Nederland) New Caledonia (Nouvelle- Cal donie) New Zealand Niger (Nijar) Norfolk Island North Korea ( ) Northern Mariana Islands Norway (Norge) Panama (Panam ) Papua New Guinea Peru (Per ) Poland (Polska) Puerto Rico R union (La R union) Romania (Rom nia) Saint Barth lemy (Saint- Barth lemy) Saint Helena Saint Kitts and Nevis Saint Lucia Saint Martin (Saint- Martin (partie fran aise))

    Saint Pierre and Miquelon (Saint- Pierre- et- Miquelon) +508 Saint Vincent and the Grenadines San Marino

    S o Tom and Pr ncipe (S o Tom e Pr ncipe)

Salary: Not Disclosed by Recruiter

Industry: IT-Hardware & Networking

Functional Area: IT Software - Embedded , EDA , VLSI , ASIC , Chip Design

Role Category:Programming & Design

Role:Team Lead/Technical Lead

Employment Type: Full Time, Permanent



UG: B.Tech/B.E. - Computers

PG:Post Graduation Not Required

Company Profile:


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