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Senior Physical Design Engineer

3 - 8 yrs
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Not Disclosed by Recruiter Posted 12 days ago Job Applicants: 26 Job Views: 163

Job Description

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    1.Candidate should have very good experience in complete PnR and Signoff tasks including Floor planning, Placement, CTS, routing, post route optimization, STA closure, Physical verification and power analysis.
    2.Candidate should have worked in multiple Tapeouts. The experience in 16nm and lower nodes is an added advantage.
    3.Candidate should have good knowledge in scripting languages like TCL and PERL.
    4.Candidate will be responsible for executing PNR tasks of the blocks and or full chip activities and also he needs to help couple of junior members in the team whenever they need some help.
    5.We have technical and Managerial ladder for the candidates and as an organization we will help the candidate to identity and grow either in technical ladder or Managerial ladder based on the candidates skill set and the interest.
    6.Candidates also will have flexibility to change the ladder later.

Salary: Not Disclosed by Recruiter

Industry: Semiconductors / Electronics

Functional Area: Other


Employment Type: Permanent Job, Full Time


Desired Candidate Profile

    Please refer to the Job description above


UG: B.Tech/B.E. - Electrical, Electronics/Telecommunication

PG:M.Tech - Any Specialization

Doctorate:Doctorate Not Required

Company Profile:

cientra tech solutions
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Job Posted by

Rahul Ravi Lead Talent Acquisition Mindlance Inc Bengaluru / Bangalore

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