Physical Design -Senior Engineers /Leads
Our client is a venture of Multi-Billion US$ Indian companies a Design and Test Engineering Service Company providing End to End Solutions from VLSI Design, Test and Product Engineering , PCB Design, Failure Analysis , Systems design, Manufacturing , Product Engineering and Embedded Solutions.
Currently we are 1800+ employees worldwide inclusive of 300+ VLSI Design Engineers.
Company has aggressive growth plan across all verticals including more than 50% Growth in the VLSI Domain year on year both Analog and Digital Side.
We are preferred vendor for most of the Semiconductor IP/ Product companies across the world.
We are Global Mutli- National Company having Engineering and Sales presences in India, Malaysia, Singapore, USA, UK, Europe and China.
We have strategic and sustainable growth plan to ensure the business stability to our valued customers and to protect the career of our employees even under disturbed Business situations. Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CSExperience: 4 to 9 years
No of Position: 20
Must be hands-on technical expert. Strong written and oral communication skills.
Experienced in deep sub-micron designs (28/14/7nm) and associated issues (manufacturability, power, signal integrity, scaling). Experienced in leading Hard-IP/HardMacro/SOC timing closure and physical design tasks with deep technical knowledge in all. Stages of the design (floor planning, placement, clock-tree-synthess CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks).
Experience in Low power and high performance design.
Experience in designing for automotive industry.
Be able and willing to mentor junior team members technical or otherwise. Should be able to lead by example.
Be able to support periodic training session and knowledge sharing sessions.
Able and willing to work with teams across sites and with cross-functional teams.
Able to collaborate, extract information and deliver results. Should have sound understanding of all the Physical Design requirements. Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
Strong debug skills and Automation savvy.
Thorough understanding of ARM -A15/A9 (and or DSP) architecture. Good understanding of mixed-signal building blocks.
Understanding of power management and its implication on physical design.
Expert in tools Cadence Encounter/Magma Talus/Synopsys ICC, Primetime, StarXT, DRC/LVS.
Contact Uday Bhaskar
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