Senior Place & Route Design Engineer
Your responsibilities include but are not limited to:
Block level place and route to design closure meeting timing, area and power constraints.
Create Block metal track plan including power grid.
Generate and Implement ECOs to fix timing, noise and EM IR violations.
Run Physical design verification flow at Block / full chip level and provide guidelines to fix LVS/DRC violations to COE owners
Participate in Methodology/flow development for blocks which include correct by construction designs
Exploring methodology improvements for better power, performance , area and overall productivity
Masters/Bachelors degree in Electrical/Electronics engineering with 7-12 years of experience in semi-custom or PNR design
Knowledge of and/or experience with industry standard PNR tools which include Synopsys ICC/ICC2, Cadence Innovus
Knowledge of and/or experience with industry standard timing and physical verification tools such as PrimeTime and Calibre
A good understanding of electrical, timing and reliability issues in deep sub micron circuit design.
Strong debug skills
Scripting experience using Perl, TCL, C-shell, Make and/or other scripting languages
Knowledge and experience with basic Unix data management and job control
Excellent written and oral communication skills
Salary: Not Disclosed by Recruiter
Functional Area: IT Software - Embedded
, Chip Design
Role Category: Programming & Design
Role: Team Lead/Technical Lead
Employment Type: Permanent Job, Full Time