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Synthesis/ STA Engineer

4 - 9 yrs
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Not Disclosed by Recruiter Openings: 1 Posted 30 days ago Job Applicants: 11 Job Views: 201

Job Description

 
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    Position: Synthesis/STA Engineer
    Location: Hyderabad
    Job Type: Permanent/Fulltime
    Experience: 5-10 yrs

    Expertise in implementation of advance timing analysis techniques.
    Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm,10nm
    Ability to understand advanced digital design architectures and clocking structures to help manage Functional/Scan/MBIST timing and physical design constraints
    Understanding of Interface timing, ability to work with the RTL team to analyze and explore timing challenges.
    Experience in formal verification RTL-to-netlist and netlist-to- netlist with DFT constraints
    Good knowledge of VLSI process and device characteristics
    Good understanding of deep submicron parasitic effects, crosstalk effects etc.TCL, perl scripting.

    Skills Required:
    STA, Timing closure, PERL

    Roles:
    Responsible for logic/physical Synthesis & timing closure at the chip and block level.
    Execute static timing analysis, synthesis, formal verification and power analysis.
    Analyze results and work with the RTL designers and place / route team to resolve issues.
    Expertise with STA tools as Primetime and Tempus
    Expertise with Synthesis tools as DC and Genus
    Formal verification (LEC), Constraint development, Lint checking

Salary: Not Disclosed by Recruiter

Industry: Semiconductors, Electronics

Functional Area: IT Software - Embedded , EDA , VLSI , ASIC , Chip Design

Role Category:Admin/Maintenance/Security/Datawarehousing

Role:Technical Support Engineer

Employment Type: Full Time, Permanent

Keyskills

Education-

UG: B.Tech/B.E. - Any Specialization, Computers

PG:M.Tech - Computers, MS/M.Sc(Science) - Computers

Doctorate:Doctorate Not Required

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Vinay Kumar Mekala Delivery Manager Assure HRLABS India Private Limited Hyderabad / Secunderabad

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