Successful candidates for this position will have:
B. Tech. / M. Tech. with 4-8 years of experience in Synthesis, STA
Expertise in synthesis of complex SoCs at block/top level and writing timing constraints for complex designs with multiple clocks and multiple voltage domains
Expertise on post layout timing closure for multiple tape outs, including timing ECOs and STA signoff
Expertise in I/O constraints developments.
Expertise in implementation of advance timing analysis techniques.
Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm,10nm
Ability to understand advanced digital design architectures and clocking structures to help manage Functional/Scan/MBIST timing and physical design constraints
Ability to work with digital and analog circuit designers to analyze and explore timing challenges involved for complex designs integrating standard cell logic with high speed custom interface circuits
Good knowledge of EDA tools from RC, DC, PT, PTSI .
Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints
Good knowledge of VLSI process and device characteristics
Good understanding of deep submicron parasitic effects, crosstalk effects etc.TCL, perl scripting"
Salary: Not Disclosed by Recruiter
Role Category:Programming & Design
Employment Type:Full Time, Permanent
Desired Candidate Profile
UG:B.Tech/B.E. - Any Specialization
PG:M.Tech - Any Specialization
Doctorate:Doctorate Not Required
Micron Technology Operations India LLP
Contact Company:Micron Technology Operations India LLP