Must have expertise in ASIC viterification methodologies and ASIC design flow
Experience working of SV and UVM methodology and knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR or similar is required, must have executed at-least 2 SoC Verification projects
Experience in any of the listed topics: UVM, formal verification, mixed-signal simulations, power-aware simulations
Experience in setting up and debugging functional and/or gate-level simulations
Experience in translating functional requirements into verification plans
Experience in developing verification environment and regression setup.
Coverage analysis and closure
Industry:
Electronic Components / Semiconductors
Department:
Engineering - Hardware & Networks
Role Category: Hardware
Role: Design Verification Engineer
Employment Type: Full Time, Permanent