Mixed Signal Design Verification Engineer

From 6 to 11 year(s) of experience
₹ Not Disclosed by Recruiter

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Posted: 13 days agoJob Applicants: Less than 10Job Views: 95

Job Description

Job Description

IP Sr AMS/MSIP Verification Lead shall be responsible for leading a small team of AMS verification engineers who shall be part of a highly motivated verification team which is responsible for AMS DV for IPs like UCIe, HBM, Aphy, PCIe, UFS etc.List of responsibilities includes but not limited to the following tasks.

Prepare and implement a robust end to end / comprehensive AMS verification test plan for IP AMS verification. Be and expert in enabling Behavioral Models for Custom analog blocks with Real Number Modelling.

Be familiar with custom circuit blocks like OPAMPs, High Speed ADCs, Constant GM Bias, CTLE, High Speed Tx, Clock DCC, High Speed Rx CTLE, VGA/DFE, Loop filter, PLL, LDO, RComp , Tx/Rx calibrations etc and be able to model them according to specifications.

Be thorough with Co-sim tools like VCS+FineSim/CustomSim and also stand alone VCD based fast spice simulation Develop any needed Unit level TB for AMS verification / work on regression enabling automation tools / methods / flows as needed independently. Be familiar with NLP flows for UPF based low power verification from AMS perspective.

Be thorough with FEV tools like LEC/Equivalence check tools for BMOD Vs Sch Eq check. Possess sharp test content creation, debugging skills and file for bugs and close on them in a timely fashion. Work with cross functional teams (analog/digital design/post-si electrical val/ high volume testing) to ensure proper AMS coverage

Qualifications

BE/ME/MTech/MS with 6 to12 years of AMS Verification experience. Candidate with prior AMS experience on High speed serial IOs like PCIe/SATA/USB/UFS is preferred. Must be well versed in AMS Co-sim and fast spice tools, and FEV/ LEC Eq tools. Must be well versed in Real Number Modelling, and or VerilogA /VAMS.

Basic Knowledge of real value modelling of channel impulse response for receiver adaptation / equalization verification is a strong plus. Basic familiarity with high level advanced receiver adaptation techniques which may include fsm or ucontroller based firm- ware driven equalization is a strong plus.

Understand basics of DV methodologies like UVM/OVM/VMM/System Verilog, constrained random stimulus generation, assertion based verification and functional coverage techniques. Knowledge of Phy IP / MAC+Phy sub-system level for protocols like PCI-E , UCIe, HBM, UFS is a strong plus.

Familiarity with RTL design aspects like Physical Coding sub layer, Physical media access blocks is a strong plus.

Education

UG:B.Tech/B.E. in Any Specialization

PG:M.Tech in Any Specialization

Company Profile

Intel

Intel Technology India Pvt.Ltd focuses on creating innovative products that advance the next generation of technology. Intel with its strong technology heritage, provides an opportunity to work on cutting-edge technology, pushing the boundaries of innovation and transforming the way people live and work.
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Contact Company:Intel

Address:.

Reference Id:JR0249848

Salary:

Not Disclosed by Recruiter

Role Category:

Hardware

Role:

Design Verification Engineer

Employment Type:

Full Time, Permanent

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