Power Integrity Engineer

From 10 to 12 year(s) of experience
₹ Not Disclosed by Recruiter

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Posted: 21 days agoJob Applicants: Less than 10Job Views: 112

Job Description

Delivers power integrity solutions for large, complex highspeed platforms, boards, packages, and silicon. Develops and analyzes power delivery networks including 2D and 3D model extraction and noise analysis across die/C4 bumps, silicon, package, sockets, and boards. Defines power grid specification and power and area targets to achieve the best balance of power integrity and performance.

Develops test structures, electrical analysis methodology and verification plans to address challenges. Performs measurements to characterize power noise profile across frequency, ground bounce, and other key metrics to verify power delivery network after design and correlate back to presilicon analysis/estimations.

Applies knowledge of power integrity design and tradeoffs to perform simulations of power network, guide package, and platform physical implementation. Ensures that ondie power noise meets SoC and other key platform ingredient functionality and performance.

Develops and delivers platformlevel power shapes and decoupling solutions as part of the platform design guide to the end customers. Derives platform level specifications from silicon specifications, ensures package/platform pathfinding to converge on feature set/form factor, and VR performance characterization.

Collaborates with the silicon integration team, die floor planners, and package design team to optimize the ondie decoupling partitions and implement the package decoupling scheme and voltage regulation for package/die.


Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Bachelor's or Master's Degree in Electrical Engineering with 10+ years of relevant industry experience or PhD in Electrical Engineering with 8-10 years of relevant experience.
Minimum 10 years' experience with each of the below skill sets:
o Proven experiences on package and board level power integrity
o Experience with power integrity modeling and analysis tools, including Hspice, powerDC, powerSI, or other similar design tools. Experience with Matlab, Mathematica, HFSS will be added advantage.
Problem solving ability to work through simulation issues, debug etc.
Familiar with DC-DC converter technology and electromagnetic field theory.

Preferred Qualifications:
Good understanding on various droop mitigation schemes, Verilog level modeling, On-chip PDN and circuit techniques, PDN to timing correlation, CAD tools - Cadence Virtuoso, Spectre, Solid scripting skills in Python/tcl.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.


UG:Any Graduate

PG:Any Postgraduate

Company Profile


Intel Technology India Pvt.Ltd focuses on creating innovative products that advance the next generation of technology. Intel with its strong technology heritage, provides an opportunity to work on cutting-edge technology, pushing the boundaries of innovation and transforming the way people live and work.
Company Info
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Contact Company:Intel


Reference Id:JR0261649


Not Disclosed by Recruiter

Role Category:



Head - Hardware Engineering

Employment Type:

Full Time, Permanent

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