DFT Engineer I

MNC Semiconductor Product

1 to 5 yrs. Bengaluru / Bangalore
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Posted on 29 Jul 2017

Job Description

Candidate will work closely with frontend and backend team to successfully implement SCAN,IDDQ and Memory BIST on MCU16 projects. He/she will be responsible for full-chip SCAN implementation, ATPG, Boundary Scan, Memory BIST and post silicon support to improve yield.

Expert knowledge of DFT architecture on complex design with multiple clock domains.

- Experience in pattern generation and simulations for Test Transition faults, Stuck-at, IDDQ, Bridging fault and Small delay defects .

- Experience in industry standard tools - Mentor Tessent suite, Synopsys DFT compiler, Prime Time etc.

- Experience in building Verification environments to simulate ATPG patterns.

- Experience of working with Teradyne and CTS tester to debug ATPG patterns on silicon.

Keyskills

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