Dft, ASIC, RTL design and verification

DFT Engineer:
1-10 year experience with Skill set : Scan insertion with Test Compression, ATPG for stuck-at and Transition faults, MBIST insertion, Memory Repair implementation and Pattern Validation, IJTAG, Boundary Scan

Design and Verification Engineer:
1-5 year experience with Skill set: Logic Desgin, RTL coding, Synthesis, Timing Check, System Verilog, UVM and scripting language.

Link to Job: http://ramictech.com/carrers-2/

Keyskills