Excellent Openings for Analog Layout

JD
To work independently on Analog layout design of block level and chip level from schematics.
Hands on experience in Analog Layout design of various designs – SerDes, LVDS, DDR Phy, PLL, Linear and Switching regulators and analog building blocks – amplifiers, comparator, oscillator, voltage and current reference circuits etc.
Good understanding of deep sub-micron and DFM issues and layout techniques
Should have work experience in CMOS process technologies – 22nm, 28nm, 45nm, 65nm etc.
Thorough working knowledge of layout design and physical verification tools - Cadence Virtuoso layout suite, Mentor Calibre, Synopsys Hercules etc.
Responsible for timely and quality execution of layout design

I

Keyskills