Physical Design Engineer

3X3 Conect

5 to 8 yrs. Bengaluru / Bangalore
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Posted on 14 Mar 2019

Job Description

• Lead block/chip level PD activities for lower technology node ( 16nm and below ).
• PD activities include floor plans, abstract view generation, Top IR, RC extraction, PNR, STA, LEC, DRCs & LVS verification.
• Process node experience to be in the range of 16nm & below (i.e.16 nm, 10 nm, 7 nm).
• Work in advanced technology nodes as listed above at GHz speeds.
• Working knowledge of Processor(CPU/GPU) is plus.
• Working knowledge of DDR/PCIe is plus

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Job Posted by

Vrushali Mahajan Sourcing Specialist 3X3 Conect Bengaluru / Bangalore

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