Physical Design Engineer

3x3 conect

5 to 8 yrs. Bengaluru / Bangalore
Apply without registration
Posted on 13 Mar 2019

Job Description

• Lead block/chip level PD activities for lower technology node ( 16 nm and below ).
• PD activities include floor plans, abstract view generation, Top IR, RC extraction, PNR, STA, LEC, DRCs & LVS verification.
• Process node experience to be in the range of 16nm & below (i.e.16 nm, 10 nm, 7 nm).
• Work in advanced technology nodes as listed above at GHz speeds.
• Working knowledge of Processor (CPU/GPU) is plus.
• Working knowledge of DDR/PCIe is plus

• BE/BTECH/MTECH with 5+ years of experience in ASIC Physical Design.
• Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies
• Experienced in Cadence (EDI) or Synopsys (ICC) and Mentor (Calibre) EDA Tools.
• Good hands-on previous experience in scripting and/or flow development preferred in one or more of Perl, Tcl, Shell scripts, Python, C


Job Posted by

Syed Omar Sourcing Specialist 3x3 Conect Bengaluru / Bangalore


IEIL has taken all reasonable steps to ensure that information on this site is authentic. Applicants are advised to research bonafides of advertisers independently. IEIL shall not have any responsibility in this regard. We also recommend that you visit Security Guidelines and Terms and Conditions for more comprehensive information on this aspect.