Physical Design Engineer

3-5 yrs experience in Physical Design Execution is required.
Independent planning and execution of Netlist-to-GDSII.
Ability to collaborate and resolve issues w.r.t. constraints validation, verification, STA, Physical design, etc.
Work on methodology with help of local and external CAD/EDA teams for faster design convergence.
Well aware of place and route methodologies and hands on experience with timing convergence.
Well versed with the level timing closure (STA), timing closure methodologies.
Tcl scripting knowledge is mandatory.
Shell / sed / awk / perl scripting knowledge preferred.
Experience/Knowledge in Chip level Timing closure.

Keyskills