senior ASIC Design and Verification Engineer

. Define micro architecture from datasheet or requirements document
· Do RTL-level design for any digital logic
· Perform module-level verification and lint checking
· Interact with verification engineers for – test plan review, coverage
debug
. Strong hands-on experience with Verilog design
· Should be able to work independently once the design
requirements are specified
· Knowledge of standard interfaces viz., AXI, AHB, Flash-Memory,
OTP, I2C/SPI is a plus
· Knowledge of vp3, perl, and EDA tools for LEC, synthesis is a plus

Keyskills