Jagadeeswari

Sectors and Skills I hire for

DFT Design , Digital Design Lead , Soc , Memory Layout , IO Characterization , Serdes , Analog Layout , IC Layout , STA , Pre silicon Emulation , Post silicon Validation HDMI , Asic , L3 , L2 L3 Development -Testing , LTE Telecom , static timing analysis , sta , netlist , Sta Clousre , Timing Closure , rtlcompiler , Soc Sta , Vlsi Sta , static timing analysis engineer

High Level, Top Mangement Level

AMD, Chelsio , Lantiq , Silicon Image, Smart Play, ON Semiconductor, Karmic, Ericsson, Qualcom, Amazon, Exponential, Emulex, Cisco, Barracuda, Infinite, Adobe, One Access, Akamai, Radisys, Mavenir, Adtran

IT- Hardware / Telecom / Technical Staff / Support, IT Software - Embedded /EDA /VLSI /ASIC /Chip Des.

IT-Hardware & Networking, Semiconductors/Electronics