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Best Infosystems Ltd 5-10 yrs Bengaluru
STA, DFT Engineer, DFT, Scanning, Atpg, Timing Closure, Bist, Perl...
- Familiarity with PD concepts/flow and assist PD team if and when required;- Good exposure to STA tool;- Good scripting skills (TCL/Perl ...
Not disclosed
Posted by HR , 29 days ago
Tessolve Semiconductor 3.9(34 reviews) 8-12 yrs Bengaluru
DSP, STA, Synthesis, Timing Closure, SoC, ARM, Mixed Signal...
- Good understanding of mixed-signal building blocks;- Experience in Low power and high performance design;- Should have sound understanding ...
Not disclosed
Posted by HR , 30+ days ago
Infinity HR Consulting Services 3-8 yrs Bengaluru
STA, Synthesis, EDA, Timing Closure, STA Engineer, SoC Encounter
- 7-10 years of hands-on experience in timing analysis;Critical hiring for STA Engineer with experience 12+ yrs with Bangalore based ...
Not disclosed
Posted by HR , 30+ days ago
Infinity HR Consulting Services 4-9 yrs Bengaluru
STA, Design Verification, Tcl / Tk, CAD, Signal Integrity...
- Desirable experience in formal / logic equivalence checking techniques;- Must have at least 5 - 8 years of experience, out of which at least 4 ...
Not disclosed
Posted by HR , 30+ days ago
Infinity HR Consulting Services 10-16 yrs Bengaluru
STA, Synthesis, EDA, Timing Closure, SoC Encounter
- 7-10 years of hands-on experience in timing analysis;Critical hiring for STA Engineer with experience 12+ yrs with Bangalore based ...
Not disclosed
Posted by HR , 30+ days ago
Infinity HR Consulting Services 7-12 yrs Bengaluru
STA, Synthesis, EDA, Timing Closure, CAD, Signal Integrity, Perl...
- Desirable experience in formal / logic equivalence checking techniques;- Must have at least 5 - 8 years of experience, out of which at least 4 ...
Not disclosed
Posted by HR , 30+ days ago
Worklia 7-12 yrs Bengaluru
sta, asic, chip, semiconductor, soc, lvs, rtl, dft, drc, pd, DMSA, vlsi...
INR 15,00,000 - 30,00,000 PA.
Posted by Shalu Ojha , 14 days ago
Worklia 7-12 yrs Bengaluru
asic, STA, chip, eda, semiconductor, UPF, rtl, dft, Synthesis, drc, pd...
INR 15,00,000 - 30,00,000 PA.
Posted by Shalu Ojha , 14 days ago
Worklia 4-9 yrs Bengaluru
asic, STA, chip, eda, semiconductor, UPF, rtl, dft, Synthesis, drc, pd...
INR 6,00,000 - 16,00,000 PA.
Posted by Shalu Ojha , 14 days ago
Worklia 4-9 yrs Bengaluru
sta, asic, chip, semiconductor, soc, lvs, rtl, dft, drc, pd, DMSA, vlsi...
INR 6,00,000 - 16,00,000 PA.
Posted by Shalu Ojha , 14 days ago
Aligarh Muslim University 4.7(44 reviews) 3-5 yrs Aligarh
Not disclosed
Posted 14 days ago
Confidential 10-15 yrs Bengaluru
STA, Floor Planning, Physical Design, Verification
- ICC, block level and some top level experience;- Working experience in 14nm or lower geometry is ...
Not disclosed
Posted by HR , 27 days ago
Best Infosystems Ltd 10-15 yrs Bengaluru
STA, ASIC, Synthesis, DFT, Verilog, Perl, TCL, Scripting
- Should have ability to debug tool /design issues;- Should be able to independently handle Synthesis/STA (timing/noise/power);Minimum ...
Not disclosed
Posted by HR , 27 days ago
Confidential 3-8 yrs Bengaluru
STA, Floor Planning, DRC, LVS, Physical Design, Verification...
Preferably who can join early would be considerable;- ICC, block level and some top level experience;- Working experience in 14nm or lower ...
Not disclosed
Posted by HR , 28 days ago
Best Infosystems Ltd 4-9 yrs Bengaluru
STA, ASIC, Synthesis, DFT, ASIC Design Engineer, Verilog, Perl, TCL...
- Should have ability to debug tool /design issues;- Should be able to independently handle Synthesis/STA (timing/noise/power);Minimum ...
Not disclosed
Posted by HR , 27 days ago
Catalyst 7-12 yrs Bengaluru
Primetime, STA, ASIC, Synthesis, Timing Closure, Design Engineering, Static...
He should be able to mentor young team member in addition to contribution as Individual contributor;- Must be able to create synthesis ...
Not disclosed
Posted by HR , 7 days ago
Inspiration Manpower Consultancy Pvt. Ltd. 3.8(5 reviews) 5-8 yrs Bengaluru
STA, Formal Verification, Synthesis, Cdc, Timing Closure, Cadence, Lec...
Experience in working/leading full-chip STA closure, defining mode requirements and corners for timing closure;Experience level: 5+ Years;Work ...
INR 8,00,000 - 17,00,000 PA.
Posted by Keerthi , 30+ days ago
Xilinx India Pvt Ltd 4.7(14 reviews) 6-11 yrs Hyderabad
memory controller, synthesis, sta, static timing analysis, usb, primetime...
To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups ...
Not disclosed
Posted by Shalini , 6 days ago
Cambio Consulting India Pvt Ltd 4-9 yrs Bengaluru, Hyderabad
STA, Backend, Synthesis, Front End, ASIC Design
1. Develop ASIC STA methodology & flows 2.Work with other stakeholders to drive STA sign-off methodologies across the company, and work ...
INR 7,00,000 - 17,00,000 PA.
Posted by Sheshagiri Rao , 15 days ago
Cambio Consulting India Pvt Ltd 4-9 yrs Bengaluru, Hyderabad
STA, ASIC, Synthesis
1. Develop ASIC STA methodology & flows 2.Work with other stakeholders to drive STA sign-off methodologies across the company, and ...
Not disclosed
Posted 15 days ago
Infinity HR Consulting Services 9-14 yrs Bengaluru
STA, Synthesis, Timing Closure, Static Timing Analysis Engineer...
- 7-10 years of hands-on experience in timing analysis;- Experience in doing SoC level timing analysis;- Should be familiar with timing analysis ...
Not disclosed
Posted by HR , 13 days ago
Amisign Technologies 10-15 yrs Bengaluru
STA, Synthesis, Physical Verification, Floor Planning, Timing Closure...
- 2- 11 years of experience in digital implementation;- Experience with 28nm and/or 16nm digital implementation and physical validation ...
Not disclosed
Posted by HR , 6 days ago
Vhunt4U 4-9 yrs Taiwan, China
Primetime, Physical Verification, DRC, Floor Planning, Timing Closure...
" Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, ...
Not disclosed
Posted by HR , 27 days ago
Vhunt4U 10-15 yrs China, Taiwan
Primetime, Physical Verification, DRC, Floor Planning, Timing Closure...
Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, ...
Not disclosed
Posted by HR , 27 days ago

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Career Edge Technologies 5-10 yrs Bengaluru
STA, VHDL, Timing closure, Digital design, SOC, Verilog, Ethernet, Business...
5 to 10 years of hands- on experience in RTL based digital design (VHDL/ Verilog) Domain Knowledge on Ethernet physical layer, MAC is an ...
Not disclosed
Posted Just Now
Sdora Consulting Pvt Ltd 3-8 yrs Bengaluru
STA, ASIC, Physical Verification, DRC, Floor Planning, Timing Analysis, PNR...
Prior experience with 28nm or lower technology nodes is desired;Good understanding of timing, clock tree, routing, and DRC/LVS issues/solutions ...
INR 3,00,000 - 8,00,000 PA.
Posted by Pramila Patel , 7 days ago
Qualcomm india pvt ltd. 4.1(102 reviews) 3-6 yrs Bengaluru
STA, ASIC, Timing closure, SOC, Manager Technology, Physical design
Job Overview As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile and IOT markets.The candidate will work ...
Not disclosed
Posted 24 days ago
SeviTech Systems Pvt Ltd 3.9(7 reviews) 10-15 yrs Noida
sta, routing, physical design, gds ii, perl scripting, CTS, netlist...
- Hands-on experience on technology nodes like 28nm, 20nm, 14nm, 10nm;- Hands-on experience in block/top level signoff STA, physical ...
Not disclosed
Posted by HR , 7 days ago
SeviTech Systems Pvt Ltd 3.9(7 reviews) 3-8 yrs Noida
STA, routing, perl scripting, CTS, Physical Design Engineer, GDS II...
- Hands-on experience on technology nodes like 28nm, 20nm, 14nm, 10nm;- Hands-on experience in block/top level signoff STA, physical ...
Not disclosed
Posted by HR , 7 days ago
SeviTech Systems Pvt Ltd 3.9(7 reviews) 5-10 yrs Bengaluru
STA, LVS, ICC, Routing, Congestion, Netlist, block level...
Hands-on experience on technology nodes like 28nm, 20nm, 14nm, 10nm;Hands-on experience in block/top level signoff STA, physical verification ...
Not disclosed
Posted by HR , 7 days ago
SeviTech Systems Pvt Ltd 3.9(7 reviews) 5-10 yrs Bengaluru
STA, Physical Verification, DRC, Floor Planning, PNR, Placement, LVS, ICC...
- Hands-on experience on technology nodes like 28nm, 20nm, 14nm, 10nm;- Hands-on experience in block/top level signoff STA, physical ...
Not disclosed
Posted by HR , 7 days ago
Catalyst 5-10 yrs Bengaluru
STA, DFT, Design Verification, Verilog HDL, Perl, RTL Coding, ASIC Design...
- 3 - 10 years hands-on IC design experience and a Bachelors degree in Electrical Engineering;- Must have experience in generating block level ...
Not disclosed
Posted by HR , 7 days ago
Assure HR Labs 5-10 yrs Pune, Noida
STA, Floor Planning, PNR, placement, Clock Tree Synthesis, Physical design,...
* Experience in mentoring junior engineers;Scripting experience in Perl, TCL, ...
Not disclosed
Posted by HR , 3 days ago
Aricent Technologies (H) Limited 3.6(402 reviews) 10-20 yrs Bengaluru, Chennai, Coimbatore
physical design, floor planning, place & floorplanning, Synthesis...
Must be highly motivated and possess excellent team spirit;Experience in handling lower tech nodes that include 40nm,28nm,etc;Must have hands ...
Not disclosed
Posted by HR , 30+ days ago
Aricent Technologies (H) Limited 3.6(402 reviews) 5-10 yrs Bengaluru, Chennai, Coimbatore
physical design, floor planning, place & floorplanning, Synthesis...
Not disclosed
Posted by HR , 30+ days ago
Catalyst 7-12 yrs Bengaluru
STA, Verification, RTL, USB Serdes - phy integration, Primetime, ASIC...
He should be able to mentor young team member in addition to contribution as Individual contributor;- Must be able to create synthesis ...
Not disclosed
Posted by HR , 29 days ago

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Amisign Technologies 10-20 yrs Bengaluru
DEO / CDO, STA, Floor Planning, PnR, Timing Closure, CAD, FinFET...
- Experience with double pattern finfet required, experience with triple pattern process nodes a plus;Education : MSEE 8+ years experience or ...
Not disclosed
Posted by HR , 6 days ago
Synopsys India Pvt. Ltd 4.1(44 reviews) 4-9 yrs Hyderabad
Primetime, PrimeTime SI, STA, design compiler, asic synthesis...
*Hands on experience with one or more of frontend implementation/Low Power implementation/Signoff/Formal verification areas ...
Not disclosed
Posted by Sarni T , 3 days ago
Synopsys India Pvt. Ltd 4.1(44 reviews) 3-8 yrs Bengaluru
synthesis, sta, physical design, physical synthesis, iccompiler...
Work in advanced technology nodes as listed above at GHz speeds required developing deep technical knowledge in one or more of ...
Not disclosed
Posted by Taufiq 9148401555 , 11 days ago
Sankalp Semiconductor Pvt. ltd 3-8 yrs Bengaluru
STA, Physical Verification, DRC, Floor Planning, PNR, Timing Closure...
Not disclosed
Posted by HR , 9 days ago
Aelfric Solutions 2-7 yrs Hyderabad
STA, Physical Verification, DRC, Floor Planning, PNR, Timing Closure...
- Should have good exposure to high frequency design convergence and exposure to physical design methodology;- Well versed with the level timing ...
Not disclosed
Posted by HR , 9 days ago
EiC Tec hsys 4-8 yrs Bengaluru
STA, DFT, Timing Closure, RTL, DRC / LVS, IR/ IVD / EM
- Should be able to construct clocks on multi-clock, synchronous and asynchronous clock domain partitions ; - Should have owned DRC/ LVS/ANT ...
Not disclosed
Posted by HR , 10 days ago
Infinity HR Consulting Services 10-15 yrs Bengaluru
STA, Physical Verification, DRC, Floor Planning, Timing Closure, PNR...
Critical Hiring for Bangalore/Delhi NCR Product based Organization. Location: Bangalore Experience: 2+yrs Job ...
Not disclosed
Posted by HR , 13 days ago
Infinity HR Consulting Services 2-7 yrs Bengaluru
STA, Physical Verification, DRC, Floor Planning, Timing Closure, PNR...
Critical Hiring for Bangalore/Delhi NCR Product based Organization. Location: Bangalore Experience: 2+yrs Job ...
Not disclosed
Posted by HR , 13 days ago
Infinity HR Consulting Services 2-4 yrs Bengaluru
STA, Cadence Encounter, LVS, Innovus, scripting, RTL2GDS, Synthesis, DFT...
- 2-4 yrs experience in EDA and/or PnR domains;- Good in scripting / flow development with good knowledge of Perl, Tcl, Shell scripts;Prefer ...
Not disclosed
Posted by HR , 10 days ago
Infinity HR Consulting Services 9-14 yrs Bengaluru
STA, Formal Verification, CTS, Synthesis, DRC, PnR, Timing Closure...
Job Description: - Full Chip Flat and Block Level Place and Route - Floor planning - Placement - CTS ...
Not disclosed
Posted by HR , 13 days ago
ONS Search 7-11 yrs Bengaluru
STA, PT, static timing analysis, Timing, Prime Time, PTSI
Requirements: 7- 10 years of hands- on experience in timing analysis. Experience in doing SoC level timing analysis. Should be familiar ...
Not disclosed
Posted 12 days ago
Wipro Limited 3.8(6218 reviews) 7-12 yrs Bengaluru
Primetime, STA, DRC, Timing Analysis, Floor Planning, Timing Closure...
The minimum engineering experience required is typically a BS degree in EE/CS with 6+ years of;Candidate must have the ability to prioritize ...
INR 25,00,000 - 40,00,000 PA.
Posted by Sridhar , 21 days ago
Xilinx India Pvt Ltd 4.7(14 reviews) 8-13 yrs Hyderabad
memory controller, synthesis, sta, static timing analysis, usb, primetime...
To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups ...
Not disclosed
Posted by Shalini , 27 days ago
Xilinx India Pvt Ltd 4.7(14 reviews) 7-12 yrs Hyderabad
memory controller, IP Design, synthesis, STA, VLSI, static timing analysis,...
Can write sdc/tcl for DC/Primetime(PT) tool for STA analysis, should be able to create synthesis constraints based on design requirements;Have ...
Not disclosed
Posted by Shalini , 27 days ago
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