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Static Timing Analysis Jobs

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Assure HR Labs 4-9 yrs Bengaluru
STA, Design Compiler, Synthesis, Timing Analysis, SOC, RTL
Position: Lead Synthesis /STA Job description: * Strong in-depth hands on experience in Synthesis, Physical Synthesis - Genus ...
Not disclosed
Posted by HR , Few Hours Ago
Assure HR Labs 10-20 yrs Bengaluru
STA, Design Compiler, Synthesis, Timing Analysis, SOC, RTL
Position: Lead Synthesis /STAJob description: * Strong in-depth hands on experience in Synthesis, Physical Synthesis - Genus DC Experience. ...
Not disclosed
Posted by HR , Few Hours Ago
Wipro Ltd 3.8(6239 reviews) 5-10 yrs Hyderabad, Hyderabad
Static Timing analysis, ASIC Synthesis
5-10 yrs experience BE/BTech Electrical/Electronic or ME/MTech in VLSI design ,>5 yrs of ASIC Synthesis and STA/timing closure experience,Experie ...
Not disclosed
Posted by synergy.updates@wipro.com , 14 days ago
Cambio Consulting India Pvt Ltd 10-18 yrs Hyderabad
STA, Physical Verification, Floor Planning, DRC, PNR, Floorplan, LVS...
Must have good communication & problem-solving skills;Have hands-on experience in latest sub-micron technologies below 20nm;Experience in ...
INR 17,00,000 - 32,00,000 PA.
Posted by Sheshagiri Rao , 30+ days ago
Aricent Technologies (H) Limited 3.6(402 reviews) 5-10 yrs Bengaluru, Chennai, Coimbatore
physical design, floor planning, place & floorplanning, Synthesis...
Not disclosed
Posted by HR , 30+ days ago
Prodigy Technovations Pvt Ltd 6-8 yrs Bengaluru
STA, GigE, FPGA Design, VLSI, USB, PCIe, VHDL, Product Testing...
The role involves contributing to the entire FPGA based product development flow starting from requirement analysis till final product testing ...
INR 18,00,000 - 20,00,000 PA.
Posted by Kempegowda , 3 days ago
Prodigy Technovations Pvt Ltd 3-5 yrs Bengaluru
STA, VHDL, FPGA Design, Synthesis, VLSI, Placement, Verilog, Altera, Static...
Experience on synthesis, placement and routing and also floor planning;Should have strong problem solving and debugging capabilities;He role ...
Not disclosed
Posted by Kempegowda , 25 days ago
Piana IT Solutions 4-9 yrs Noida
EDA tool development, static timing analysis, C / C++...
Looking to hire Software Engineer with minimum 2+ years of experience. Applications from a candidate with MTECH/BTECH/CS from Top Institutes ...
Not disclosed
Posted by HR , 3 days ago
Amisign Technologies 10-15 yrs Bengaluru
Primetime, Shell Scripting, Perl, Physical Design, Static Timing Analysis...
- Experience with constraint-checking tools a plus;- Demonstrates good analysis and problem-solving skills;- Prior experience converging large ...
Not disclosed
Posted by HR , 10 days ago
Infinity HR Consulting Services 6-11 yrs Bengaluru
Synthesis, DDR, Timing Closure, USB, SoC, Physical Design...
- 7-10 years of hands-on experience in timing analysis;- Experience in doing SoC level timing analysis;- Should be familiar with timing analysis ...
Not disclosed
Posted by HR , 3 days ago
Vhunt4U 10-15 yrs China, Taiwan
Primetime, Physical Verification, DRC, Floor Planning, Timing Closure...
Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, ...
Not disclosed
Posted by HR , 30+ days ago
Xilinx India Pvt Ltd 4.7(14 reviews) 7-12 yrs Hyderabad
memory controller, IP Design, synthesis, STA, VLSI, static timing analysis,...
Can write sdc/tcl for DC/Primetime(PT) tool for STA analysis, should be able to create synthesis constraints based on design requirements;Have ...
Not disclosed
Posted by Shalini , 30+ days ago

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Caelus Technologies Limited 5-8 yrs China, Hong Kong
FPGA, Cadence, engineer, CMOS, VHDL, Synthesis, Timing Closure...
* Experience with scan chain vector generation and verification;* Must be able to work independently according to schedules and be team player ...
USD 60,000 - 75,000 PA.
Posted 10 days ago
Infinity HR Consulting Services 3-8 yrs Bengaluru
STA, Synthesis, DDR, Timing Analysis, Timing Closure, USB, Physical Design,...
- hands-on experience in timing analysis;- Experience in doing SoC level timing analysis;- Should be familiar with timing analysis for ...
Not disclosed
Posted by HR , 3 days ago
Synopsys India Pvt. Ltd 4.1(44 reviews) 4-9 yrs Hyderabad
Primetime, PrimeTime SI, STA, design compiler, asic synthesis...
*Hands on experience with one or more of frontend implementation/Low Power implementation/Signoff/Formal verification areas ...
Not disclosed
Posted by Sarni T , Today
Synapse Techno Design Innovations Pvt Ltd 3-8 yrs Bengaluru
STA, Timing Closure, Static Timing Analysis, Perl, TCL, Synopsys, Synthesis...
Successful tape out experience of multiple complex chips at 65 or 45 nm;Note - Onsite H1B Opportunity for Engineers having 7+ Years of ...
Not disclosed
Posted by Amit Hotkar , Today
Mobiveil, Inc. 4-6 yrs Bengaluru
STA, DFT, Email, static timing analysis, level, SOC...
Not disclosed
Posted 10 days ago
Vhunt4U 4-9 yrs Taiwan, China
Primetime, Physical Verification, DRC, Floor Planning, Timing Closure...
" Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, ...
Not disclosed
Posted by HR , 30+ days ago
Infinity HR Consulting Services 2-5 yrs Delhi NCR, Greater Noida
IP Design, IP Design Engineer, STA, Synthesis, USB, RTL Development, PCIe...
- Hands on experience on RTL development as well as FE tools such as Synthesis, STA, Formal equivalence etc is needed;- Prior experience in ...
Not disclosed
Posted by HR , 3 days ago
GLOBALFOUNDRIES Inc 4.3(13 reviews) 2-5 yrs Bengaluru
Electrical engineering, STA, Semiconductor, Simulation, Digital design...
Job Description Princ Eng Design Enablement Job Number: 19002702 Digital implementation / Digital ...
Not disclosed
Posted by HR , Few Hours Ago
Infinity HR Consulting Services 10-15 yrs Bengaluru
DDR, USB, SoC, design, Cadence Encounter, Static Timing Analysis, PCIe...
- 7-10 years of hands-on experience in timing analysis;- Experience in doing SoC level timing analysis;- Should be familiar with timing analysis ...
Not disclosed
Posted by HR , 3 days ago
EiC Tec hsys 4-8 yrs Bengaluru
RTL, STA, DRC / LVS, Timing Closure, DFT, IR/ IVD / EM
- Should be able to construct clocks on multi-clock, synchronous and asynchronous clock domain partitions ; - Should have owned DRC/ LVS/ANT ...
Not disclosed
Posted by Eic Tech Sys , Few Hours Ago
Ambit Semiconductors 2-6 yrs Bengaluru, Hyderabad
Backend, Timing closure, static timing analysis, Manager Technology, Perl...
Not disclosed
Posted 6 days ago
Link Talent & Management Services 4-9 yrs Hyderabad
pg planning, Physical Verification, Synthesis, Floor Planning...
INR 5,00,000 - 15,00,000 PA.
Posted by Mayuri , 20 days ago
SeviTech Systems Pvt Ltd 3.9(7 reviews) 5-10 yrs Bengaluru
STA, Formal Verification, Synthesis, DFT, VLSI, Timing Closure, EDA Tools...
Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm,10nm;Good understanding of deep submicron parasitic effects, crosstalk ...
Not disclosed
Posted by HR , 11 days ago
Vhunt4U 4-8 yrs Bengaluru, Kochi
VHDL, ASIC Synthesis, Axi, Verilog, Static Timing Analysis, Perl, Ahb, PCIE...
Hands-on experience and expert-level knowledge in SoC integration of ARM core based designs;Hands-on experience and expert-level knowledge in ...
Not disclosed
Posted by HR , 27 days ago
GLOBALFOUNDRIES Engineering Private Limited 6-10 yrs Bengaluru
Physical Verification, Floor Planning, Placement, AWK, Shell Scripting...
Not disclosed
Posted by HR , 30+ days ago
TechPoint Solutions (India) Pvt. Ltd. 4-9 yrs Hyderabad
STA, Formal Verification, DFT, Synthesis, Timing Analysis, shell, netlist...
Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm,10nm;Please go through the job requirement we have with one of our ...
Not disclosed
Posted by Ravi Kumar , 3 days ago
Infinity HR Consulting Services 12-15 yrs Bengaluru
Synthesis, DDR, Timing Closure, USB, SoC, Physical Design...
- 7-10 years of hands-on experience in timing analysis;- Experience in doing SoC level timing analysis;- Should be familiar with timing analysis ...
Not disclosed
Posted by HR , 30+ days ago
ANALOG DEVICES INDIA PRIVATE LIMITED 3.6(12 reviews) 6-11 yrs Bengaluru
STA, Interpersonal Communication, Communication Skills, Design Development,...
Responsibilities: Develop and drive methodologies that enable Implementation, power, rail and static timing analysis of digital/mixed ...
Not disclosed
Posted by Sowmya Nihar , 5 days ago
Assure HR Labs 4-9 yrs Bengaluru, Hyderabad, Noida
Primetime, STA, Formal Verification, DFT, Synthesis, Timing Closure, Static...
Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm,10nm;Good understanding of deep submicron parasitic effects, crosstalk ...
Not disclosed
Posted by HR , 3 days ago
Infinity HR Consulting Services 9-14 yrs Bengaluru
STA, Synthesis, EDA, Timing Analysis, Timing Closure, Cadence Encounter...
- hands-on experience in timing analysis;- Experience in doing SoC level timing analysis;- Should be familiar with timing analysis for ...
Not disclosed
Posted by HR , 3 days ago
Infinity HR Consulting Services 10-15 yrs Bengaluru
STA, Physical Verification, DRC, Floor Planning, Timing Closure, PNR...
Critical Hiring for Bangalore/Delhi NCR Product based Organization. Location: Bangalore Experience: 2+yrs Job ...
Not disclosed
Posted by HR , 3 days ago
Infinity HR Consulting Services 2-7 yrs Bengaluru
STA, Physical Verification, DRC, Floor Planning, Timing Closure, PNR...
Critical Hiring for Bangalore/Delhi NCR Product based Organization. Location: Bangalore Experience: 2+yrs Job ...
Not disclosed
Posted by HR , 3 days ago
Catalyst 7-12 yrs Bengaluru
Primetime, STA, ASIC, Synthesis, Timing Closure, Design Engineering, Static...
He should be able to mentor young team member in addition to contribution as Individual contributor;- Must be able to create synthesis ...
Not disclosed
Posted by HR , 11 days ago
Infinity HR 10-18 yrs Pune
Circuit Designing, Design Verification, Floor Planning, Timing Closure...
- Good knowledge of standard cell libraries - circuit design and cell layout;- Good knowledge of VLSI process and device characteristics, to ...
Not disclosed
Posted by HR , 30+ days ago

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Infinity HR Consulting Services 10-15 yrs Bengaluru
STA, Synthesis, Timing Closure, USB, Perl, TCL, Synopsys, SoC Encounter
- 7-10 years of hands-on experience in timing analysis;- Experience in doing SoC level timing analysis;- Should be familiar with timing ...
Not disclosed
Posted by HR , 30+ days ago
Le Human Resources Solutions Pvt Ltd 4-8 yrs Bengaluru, Hyderabad
Primetime, Physical Verification, Floor Planning, Timing Closure...
4+ years of experience to lead and manage a team of physical design engineers with expertise on Partitioning, IO ring preparation, Floor ...
Not disclosed
Posted 30+ days ago
Cyient Limited 3.6(1128 reviews) 6-11 yrs Bengaluru, Hyderabad
Primetime, Physical Verification, Floor Planning, Timing Closure...
Not disclosed
Posted by Vijay Krishna , 30+ days ago
eInfochips Limited 3-8 yrs Delhi NCR, Ahmedabad
synthesis, sta, physical design, floorplanning, icc, floorplan, routing...
This job involves good written and verbal skills;Technically sound & good team player;Preferred Tool experience on Synopsys ICC or SoC ...
Not disclosed
Posted by Shikha Singh , Today
Aricent Technologies (H) Limited 3.6(402 reviews) 10-20 yrs Bengaluru, Chennai, Coimbatore
physical design, floor planning, place & floorplanning, Synthesis...
Must be highly motivated and possess excellent team spirit;Experience in handling lower tech nodes that include 40nm,28nm,etc;Must have hands ...
Not disclosed
Posted by HR , 30+ days ago
Xilinx India Pvt Ltd 4.7(14 reviews) 6-11 yrs Hyderabad
memory controller, synthesis, sta, static timing analysis, usb, primetime...
To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups ...
Not disclosed
Posted by Shalini , 10 days ago
Infinity HR Consulting Services 9-14 yrs Bengaluru
STA, Synthesis, Timing Closure, Static Timing Analysis Engineer...
- 7-10 years of hands-on experience in timing analysis;- Experience in doing SoC level timing analysis;- Should be familiar with timing analysis ...
Not disclosed
Posted by HR , 3 days ago
Assure HR Labs 5-10 yrs Pune, Noida
STA, Floor Planning, PNR, placement, Clock Tree Synthesis, Physical design,...
* Experience in mentoring junior engineers;Scripting experience in Perl, TCL, ...
Not disclosed
Posted by HR , 3 days ago
Xilinx India Pvt Ltd 4.7(14 reviews) 8-13 yrs Hyderabad
memory controller, synthesis, sta, static timing analysis, usb, primetime...
To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups ...
Not disclosed
Posted by Shalini , 30+ days ago
Micron Technology Operations India LLP 5-9 yrs Hyderabad
rtl design, timing analysis, sta, synthesis, design verification...
Not disclosed
Posted by HR , Today
Cyient Limited 3.6(1128 reviews) 7-12 yrs Bengaluru, Hyderabad
Primetime, Physical Verification, Floor Planning, Timing Closure...
Not disclosed
Posted by Vijay Krishna , 30+ days ago
Qualcomm india pvt ltd. 4.1(102 reviews) 5-8 yrs Bengaluru
Computer science, STA, Timing closure, static timing analysis, Electronics,...
Not disclosed
Posted 6 days ago
Catalyst 7-12 yrs Bengaluru
STA, Verification, RTL, USB Serdes - phy integration, Primetime, ASIC...
He should be able to mentor young team member in addition to contribution as Individual contributor;- Must be able to create synthesis ...
Not disclosed
Posted by HR , 30+ days ago
HCL Technologies Limited 3.7(7059 reviews) 5-10 yrs Bengaluru, Chennai, Hyderabad, Greater Noida
synthesis, sta, primetime, place & route, floorplan, floor planning...
Preferably experience in 20 nm, 14 nm flows; Experience: 5 to 15 yrs; Total experience:;Relevant experience in ...
Not disclosed
Posted by Arun Vikram , 3 days ago
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