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Timing Closure Jobs

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Catalyst 7-12 yrs Bengaluru
Static Timing Analysis, Primetime, STA, RTL Design, Timing Closure...
He should be able to mentor young team member in addition to contribution as Individual contributor;- Must be able to create synthesis ...
Not disclosed
Posted by HR , 1 day ago
Catalyst 7-12 yrs Bengaluru
Physical Design, Timing Closure, Timing Analysis, Signal Integrity...
degree in Electrical Engineer, Computer Engineering or Computer Science with at least 14+ years of ASIC experience in design, verification, and ...
Not disclosed
Posted by HR , 1 day ago
Vhunt4U 3-8 yrs Bengaluru, Hyderabad, Pune, Noida, Kochi, Malaysia, Singapore
DRC, Timing Closure, Primetime, Floor Planning, Static Timing Analysis...
Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, ...
Not disclosed
Posted by HR , 14 days ago
Confidential 4-9 yrs Bengaluru
Timing Closure, Physical Design, DRC, LVS, Physical Verification...
- Expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep- sub micron processes required ...
Not disclosed
Posted by HR , 27 days ago
iRageCapital 5-10 yrs Mumbai
System Verilog, C, VHDL, RTL Coding, Altera, FPGA, Xilinx, Hardware Design,...
- Work experience around (actual RTL coding done in Verilog/VHDL or at the least has picked up ownership;- Experience in optimizing Verilog/ ...
Not disclosed
Posted by Alok Parasrampuria , 5 days ago
Nastech Consulting 3-8 yrs Bengaluru
PNR, Timing Closure, Physical Design, STA, Floor Planning, DRC...
- Should be able to provide clear directions to the team wrt PNR issues Drive methodology with help of local and external CAD/EDA teams for ...
Not disclosed
Posted by HR , 5 days ago
Le Human Resources Solutions Pvt Ltd 10-15 yrs Bengaluru
physical design, floor planning, pnr, timing closure, timing analysis...
10+ years of experience to lead and manage a team of physical design engineers with expertise on Partitioning, IO ring preparation, ...
INR 20,00,000 - 35,00,000 P.A.
Posted by Roshni , 4 days ago
Best Infosystems Ltd. 3.6(18 reviews) 5-10 yrs Bengaluru
DFT, Atpg, Bist, STA, Perl, Timing Closure, TCL, Scanning, Verification...
- Familiarity with PD concepts/flow and assist PD team if and when required;- Good exposure to STA tool;- Good scripting skills (TCL/Perl ...
Not disclosed
Posted by HR , 13 days ago
Core Edge Solutions  7-12 yrs Bengaluru
ASIC, Verification, VMM, OVM, System Verilog, UVM, Timing Closure, RTL...
This position requires at least 8 yrs of relevant industry experience;Prior Experience of verification of complex SoCs / IPs in a leading role ...
Not disclosed
Posted by Sheetal , 5 days ago
Nastech Consulting 9-14 yrs Bengaluru, Ahmedabad
PNR, Timing Closure, Physical Design, STA, DRC, Floor Planning...
- Should be able to provide clear directions to the team wrt PNR issues Drive methodology with help of local and external CAD/EDA teams for ...
Not disclosed
Posted by HR , 26 days ago
Vhunt4U 5-8 yrs Singapore, Malaysia
DRC, Physical Design, Timing Closure, Floor Planning, Primetime...
- Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, ...
Not disclosed
Posted by HR , 13 days ago
eInfochips Limited 6-8 yrs Sunnyvale
STA, Timing Closure, PNR, Digital Design, Synthesis, Formal Verification...
Should be able to do full chip implementation of complex SoCs (RTL-to-GDSII) , but it is not must;Incumbent has extensive knowledge and ...
Not disclosed
Posted by Flemy John , 26 days ago
GUV Solutions 8-12 yrs Ahmedabad, Bengaluru, Noida
timing closure, physical design, floor planning, sta, synthesis...
3 Technologies from 28nm, 20nm, 14nm, 10nm. - Block level floor planning, power planning and IR drop analysis. - Timing ...
Not disclosed
Posted by HR , 26 days ago
eInfochips Limited 8-13 yrs Bengaluru
physical design, timing closure, floorplan, placement, tcl, icc, routing...
This job involves good written and verbal skills;Technically sound & good team player;Preferred Tool experience on Synopsys ICC or SoC ...
Not disclosed
Posted by Shikha Singh , Today
Careernet Technologies Pvt Ltd 4.0(10 reviews) 1-6 yrs Delhi NCR, Bengaluru
ASIC Synthesis, soc synthesis, rtl synthesis, rtl timing closure
Should have a fair idea of developing chip constraints working with RTL and DFT teams;Knowledge of tcl and perl scripting is a must;Should have ...
Not disclosed
Posted by Chandrani Raychaudhury , 4 days ago
 Catalyst 10-16 yrs Bengaluru
ASIC, RTL, Synthesis, Timing Closure, Physical Design, DDR, EDA, Synopsys...
degree in Electrical Engineer, Computer Engineering or Computer Science with at least 14+ years of ASIC experience in design, verification, and ...
Not disclosed
Posted by HR , 5 days ago
SeviTech Systems Private Limited 3.7(6 reviews) 5-10 yrs Sweden
Static Timing Analysis, STA, Synthesis, timing closure
Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm,10nm;Good understanding of deep submicron parasitic effects, crosstalk ...
Not disclosed
Posted by Priyanka Srivastava , 29 days ago
Classic Search Pvt Ltd 8-13 yrs Bengaluru
STA, Synthesis, formal verification, Timing, Timing closure...
Experience working with cross functional global teams;Familiarity with PD concepts/flow and assist PD team if and when required;Expertise in ...
Not disclosed
Posted by HR , 20 days ago
Confidential 4-9 yrs Bengaluru
Timing Closure, Physical Design, DRC, LVS, Physical Verification...
- Expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep- sub micron processes required ...
Not disclosed
Posted by HR , 7 days ago
Best Infosystems Ltd. 3.6(18 reviews) 5-10 yrs Bengaluru
DRC, Physical Design, Timing Closure, LVS, DFM, Lec, Design Verification...
Lead physical design and physical design verification activities across the various projects. - Own project specific flow setup and ...
Not disclosed
Posted by HR , 13 days ago
Core Edge Solutions  3-8 yrs Bengaluru
RTL Design, ASIC, Timing Closure, Verification, Verilog, System Verilog...
Should have good understanding of the design concepts for design having multiple clocks & clock domains & also related timings / timing ...
Not disclosed
Posted by Sheetal , 5 days ago
GUV Solutions 3-8 yrs Ahmedabad, Bengaluru, Noida
timing closure, physical design, floor planning, sta, synthesis...
3 Technologies from 28nm, 20nm, 14nm, 10nm. - Block level floor planning, power planning and IR drop analysis. - Timing ...
Not disclosed
Posted by HR , 26 days ago
Catalyst 7-12 yrs Bengaluru
Physical Design, Timing Closure, Timing Analysis, Signal Integrity...
degree in Electrical Engineer, Computer Engineering or Computer Science with at least 14+ years of ASIC experience in design, verification, and ...
Not disclosed
Posted by HR , 26 days ago
Career Maker 9-13 yrs Bengaluru
Verilog, VHDL, FPGA Design, RTL Design, ASIC, Synthesis, Timing Closure...
Experience : 8 to 12 years of experience in reputed product based Semi conductor companies;- Prior RTL design experience is required;- ASIC/FPGA ...
Not disclosed
Posted by HR , 5 days ago

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Synopsys India Pvt. Ltd 4.1(42 reviews) 3-8 yrs Bengaluru, Delhi NCR, Noida
physical design, sta, timing closure, pnr, synopsys, placement, routing, pd...
Must also demonstrate knowledge of the Synopsys tools, flows and methodologies required to execute physical design projects;- has experience in ...
Not disclosed
Posted by Shalu Sisodia , 4 days ago
Career Maker 11-15 yrs Bengaluru
PNR, Physical Design, Timing Closure, STA, DRC, Floor Planning, LVS...
- Well versed with the level timing closure (STA), timing closure methodologies, ECO generation and predictable convergence;- Should have good ...
Not disclosed
Posted by HR , 5 days ago
eInfochips Limited 6-7 yrs Sunnyvale
Physical Design, Timing Closure, VLSI Design, STA, Digital Design...
Candidate should have 5+ years of lower geometry physical design experience and over 6 to 8 years of relevant experience in complex ASIC/SOC ...
Not disclosed
Posted by Flemy John , 26 days ago
Catalyst 7-12 yrs Bengaluru
Static Timing Analysis, Primetime, STA, RTL Design, Timing Closure...
He should be able to mentor young team member in addition to contribution as Individual contributor;- Must be able to create synthesis ...
Not disclosed
Posted by HR , 15 days ago
 Enlist Management Consultants Private Limited 3.7(14 reviews) 8-12 yrs Bengaluru
Physical Design, Floor Planning, Timing Closure, Synthesis...
Job Description : - Technologies from 28nm, 20nm, 14nm, 10nm. - Block level floor planning, power ...
Not disclosed
Posted by Sundaresan T , 8 days ago
Elveego Circuits Pvt. Ltd 2-7 yrs Bengaluru
System Verilog, Axi, Ahb, RTL Coding, RTL Design, ASIC Design, FPGA, STA...
Should have good understanding of the design concepts for design having multiple clocks & clock domains & also related timings / timing ...
Not disclosed
Posted by Geeta SK , 22 days ago
eInfochips Limited 3-8 yrs Delhi NCR, Ahmedabad
physical design, floorplan, timing closure, placement, tcl...
This job involves good written and verbal skills;Technically sound & good team player;Preferred Tool experience on Synopsys ICC or SoC ...
Not disclosed
Posted by Shikha Singh , 1 day ago
eInfochips Limited 5-10 yrs Bengaluru, Ahmedabad
RTL Coding, FPGA Design, RTL Design, ASIC Design, Detailing, Timing Closure...
Should have good understanding of the design concepts for design having multiple clocks & clock domains & also related timings / timing ...
Not disclosed
Posted by Shikha Singh , 1 day ago
iRageCapital 5-10 yrs Mumbai
system verilog, vhdl, c, rtl coding, altera, fpga, xilinx, hardware design,...
- Work experience around (actual RTL coding done in Verilog/VHDL or at the least has picked up ownership;- Experience in optimizing Verilog/ ...
Not disclosed
Posted by Alok Parasrampuria , 24 days ago
eInfochips Limited 8-13 yrs Bengaluru
Physical Design, Timing Closure, Floorplan, Placement, Signal Integrity...
This job involves good written and verbal skills;Technically sound & good team player;Preferred Tool experience on Synopsys ICC or SoC ...
Not disclosed
Posted by Shikha Singh , 1 day ago
Sankalp Semiconductor Pvt. ltd 7-12 yrs Bengaluru, Ahmedabad
uvm, rtl design, design verification, pcie, sta, synopsys, dft, serdes, DDR...
Experience : 7 to 12 years;Experience in Digital module micro-architecture and design;Good knowledge of Synthesis, STA and DFT aware design ...
Not disclosed
Posted by Vidya Naik , 19 days ago
eInfochips Limited 13-14 yrs Cedar Rapids
RTL Coding, FPGA Design, ASIC Design, Timing Closure, Front End Design
Should have good understanding of the design concepts for design having multiple clocks & clock domains & also related timings / timing ...
Not disclosed
Posted by Flemy John , 25 days ago

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Best Infosystems Ltd 3.6(18 reviews) 6-11 yrs Bengaluru
DRC, Physical Design, Timing Closure, LVS, DFM, Lec, Design Verification...
Physical Design Engineer - Verification (4-12 yrs) - Lead physical design and physical design verification activities across the ...
Not disclosed
Posted by HR , 26 days ago
Best Infosystems Ltd 3.6(18 reviews) 6-11 yrs Bengaluru
DFT, Atpg, Bist, STA, Perl, Timing Closure, TCL, Scanning, Verification...
- Familiarity with PD concepts/flow and assist PD team if and when required;- Good exposure to STA tool;- Good scripting skills (TCL/Perl ...
Not disclosed
Posted by HR , 26 days ago
Best Infosystems Ltd 3.6(18 reviews) 5-10 yrs Bengaluru
DFT, Atpg, Bist, STA, Perl, Timing Closure, TCL, Scanning, Verification...
- Familiarity with PD concepts/flow and assist PD team if and when required;- Good exposure to STA tool;- Good scripting skills (TCL/Perl ...
Not disclosed
Posted by HR , 26 days ago
AIT GLOBAL INDIA PVT LTD. 3.8(13 reviews) 2-4 yrs Pune
Recruitment, Screening, Interview Coordination, Sourcing...
Responsible for achieving a good conversion ratio of submittals (quality of submission) into interview and ...
INR 2,00,000 - 3,50,000 P.A. Depends upon the Skill set of ...
Posted by AIT INDIA , 5 days ago
Shell Info Technologies Private Limited 3.9(16 reviews) 5-10 yrs Japan
Timing Closure, Physical Design, Floor Planning, STA, TCL...
INR 1 Cr & above P.A.
Posted by Syed , 4 days ago
Best Infosystems Ltd. 3.6(18 reviews) 8-12 yrs Bengaluru
DFT, Atpg, Bist, STA, Perl, Timing Closure, TCL, Scanning, Verification...
- Familiarity with PD concepts/flow and assist PD team if and when required Own full chip responsibilities;- Good exposure to STA tool;- Good ...
Not disclosed
Posted by HR , 13 days ago
eInfochips Limited 3-8 yrs Delhi NCR
Physical Design, Floorplan, Timing Closure, Placement, TCL...
This job involves good written and verbal skills;Technically sound & good team player;Preferred Tool experience on Synopsys ICC or SoC ...
Not disclosed
Posted by Shikha Singh , 5 days ago
Triadss Tech Solutions 3.5(15 reviews) 6-10 yrs Bengaluru
Timing Closure, Physical Design, Floor Planning, STA, Synthesis...
Physical Design JD : - Technologies from 28nm, 20nm, 14nm, 10nm. - Block level floor planning, power planning and IR drop ...
Not disclosed
Posted by HR , 11 days ago
Career Maker 5-10 yrs Bengaluru
PNR, Physical Design, DRC, Timing Closure, Floor Planning, STA...
- Well versed with the level timing closure (STA), timing closure methodologies, ECO generation and predictable convergence;- Should have good ...
Not disclosed
Posted by HR , 5 days ago
Best Infosystems Ltd 3.6(18 reviews) 5-10 yrs Bengaluru
drc, physical design, timing closure, lvs, dfm, lec, design verification...
- Lead physical design and physical design verification activities across the various projects. - Own project specific flow setup and ...
Not disclosed
Posted by HR , 26 days ago
Best Infosystems Ltd 3.6(18 reviews) 8-12 yrs Bengaluru
DFT, Atpg, Bist, STA, Perl, Timing Closure, TCL, Scanning, Verification...
- Familiarity with PD concepts/flow and assist PD team if and when required Own full chip responsibilities;- Good exposure to STA tool;- Good ...
Not disclosed
Posted by HR , 26 days ago
Triadss Tech Solutions 3.5(15 reviews) 4-8 yrs Bengaluru
PNR, Timing Closure, Physical Design, DRC, Timing Analysis, LVS, STA...
- Prior experience with 28nm or lower technology nodes is desired;- Good understanding of timing, clock tree, routing, and DRC/LVS issues/solutio ...
Not disclosed
Posted by HR , 11 days ago
Avenues Resources Consultants 8-10 yrs Noida
timing closure, static timing analysis, design, product validation, product...
Travel required : As per business requirement;Compensation & Benefits : Market Driven; Commensurate with the candidates experience ...
Not disclosed
Posted by Vishak Joseph , 4 days ago
Vhunt4U 10-15 yrs Bengaluru, Hyderabad, Pune, Noida, Malaysia, Singapore
DRC, Timing Closure, Primetime, Floor Planning, Static Timing Analysis...
Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, ...
Not disclosed
Posted by HR , 14 days ago
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