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Timing Closure Jobs in Bangalore

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SeviTech Systems Pvt Ltd 5-10 yrs Bengaluru
Keyskills:
Timing Closure, Physical Design, STA Engineer, STA, VLSI, TCL...
Job Description: - Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm,10nm;- Good understanding of ...
Not disclosed
Posted by Priyanka Srivastava , 29 days ago
Mulya Consulting 7-12 yrs Bengaluru, Ahmedabad
Keyskills:
physical design, sta, ssta, static timing analysis, cts, cadence, synopsys,...
Job Description: Candidate is expected to have expertise in either Cadence or Synopsys flows and should be capable of ...
Not disclosed
Posted by Mr. M.Udaya Bhaskar , 6 days ago
eInfochips Limited 3-8 yrs Bengaluru, Hyderabad
Keyskills:
physical design, floorplan, timing closure, placement, tcl...
Job Description: This job involves good written and verbal skills;Technically sound & good team player;Preferred Tool ...
Not disclosed
Posted by Shikha Singh , 1 day ago
MY Search 3-8 yrs Bengaluru
Keyskills:
DRC, Timing Closure, Floorplan, Physical Verification, Physical Design...
Job Description: - Must have expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules ...
Not disclosed
Posted by HR , 1 day ago
Career Maker 11-15 yrs Bengaluru
Keyskills:
PNR, Physical Design, DRC, Timing Closure, Floor Planning, STA...
Job Description: - Well versed with the level timing closure (STA), timing closure methodologies, ECO generation and ...
Not disclosed
Posted by HR , 25 days ago
VVDN Technologies Private Limited 3.6(70 reviews) 2-7 yrs Bengaluru, Chennai, Kochi
Keyskills:
Verilog, VHDL, FPGA, Digital Design, Xilinx, Design Verification...
Job Description: Experience can be from Networking/Video/Data Acquisition ...
Not disclosed
Posted by Dinkil K Muringathery , 5 days ago
eInfochips Limited 5-10 yrs Bengaluru, Ahmedabad
Keyskills:
RTL Coding, FPGA Design, RTL Design, ASIC Design, Detailing, Timing Closure...
Job Description: Should have good understanding of the design concepts for design having multiple clocks & clock ...
Not disclosed
Posted by Shikha Singh , 1 day ago
Qualcomm india pvt ltd. 4.1(72 reviews) 2-7 yrs Bengaluru
Keyskills:
Timing Closure, Floorplan, Primetime, DRC, ASIC Synthesis, Physical Design,...
Job Description: Experience in all aspects of implementation like, area efficient and low power, timing closure, ECO ...
Not disclosed
Posted by Sineesh P Simon , 29 days ago
Vhunt4U 4-9 yrs Hyderabad, Bengaluru, Noida, Malaysia, Singapore
Keyskills:
DRC, Timing Closure, Primetime, Floor Planning, Static Timing Analysis...
Job Description: " Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, ...
Not disclosed
Posted by HR , Today
Graphene Semiconductor Services Pvt. Ltd. 2-7 yrs Bengaluru, Singapore
Keyskills:
DRC, Floorplan, Timing Closure, Physical Design, LVS, Physical Verification...
Job Description: - Should have worked on or have tapeout experience in 28nm, 16FF, 14FF;Experience in 10nm and 7nm will ...
15,00,000 - 30,00,000 P.A.
Posted by Sunitha.L , 6 days ago
MediaTek Bangalore Private Limited 3.5(6 reviews) 5-10 yrs Bengaluru(Bellandur)
Keyskills:
DRC, LVS, Physical Design, Physical Verification, STA, Cadence...
Job Description: 5+ years of hands on experience in physical design of high performance design with frequencies > 2 ...
Not disclosed
Posted by MediaTek Bangalore , 29 days ago
eInfochips Limited 5-10 yrs Bengaluru, Ahmedabad
Keyskills:
RTL Coding, FPGA Design, RTL Design, ASIC Design, Detailing, Timing Closure...
Job Description: Should have good understanding of the design concepts for design having multiple clocks & clock ...
Not disclosed
Posted by Flemy John , 12 days ago

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Nastech Consulting 3-8 yrs Ahmedabad, Bengaluru
Keyskills:
PNR, Timing Closure, Physical Design, STA, DRC, Floor Planning...
Job Description: - Should be able to provide clear directions to the team wrt PNR issues Drive methodology with help of ...
Not disclosed
Posted by HR , 26 days ago
Sandisk India 4.6(12 reviews) 3-7 yrs Bengaluru
Keyskills:
ASIC, SOC, DFT, Timing closure, EDA tools, Manager Technology, Debugging...
Job Description: Job Description Staff Engineer, ASIC Development Engineering Bangalore, ...
Not disclosed
Posted by HR , 20 days ago
End2end Consultants 5-10 yrs Bengaluru
Keyskills:
drc, timing closure, floorplan, physical verification, floor planning...
Job Description: - Skill and experience in scripting using Tcl or Perl is highly ...
Not disclosed
Posted by Vishal Chopra , 19 days ago
Vhunt4U 10-16 yrs Bengaluru, Hyderabad
Keyskills:
DRC, Physical Design, Timing Closure, Floor Planning, Primetime...
Job Description: Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, ...
Not disclosed
Posted by HR , 6 days ago
Vhunt4U 4-9 yrs Bengaluru, Hyderabad
Keyskills:
DRC, Physical Design, Timing Closure, Floor Planning, Primetime...
Job Description: - Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, ...
Not disclosed
Posted by HR , 6 days ago
Catalyst 9-14 yrs Bengaluru
Keyskills:
Static Timing Analysis, Primetime, STA, RTL Design, Timing Closure...
Job Description: He should be able to mentor young team member in addition to contribution as Individual contributor ...
Not disclosed
Posted by HR , 26 days ago
Infinity HR Consulting Services 9-14 yrs Bengaluru
Keyskills:
Timing Closure, Physical Design, STA, Timing Analysis, Synthesis...
Job Description: - hands-on experience in timing analysis;- Experience in doing SoC level timing analysis;- Should be ...
Not disclosed
Posted by HR , 18 days ago
Infinity HR Consulting Services 6-11 yrs Bengaluru
Keyskills:
Timing Closure, Physical Design, STA, Static Timing Analysis, Synthesis...
Job Description: - 7-10 years of hands-on experience in timing analysis;- Experience in doing SoC level timing analysis ...
Not disclosed
Posted by HR , 18 days ago
Synapse Techno Design Innovations Pvt Ltd 3-8 yrs Bengaluru, United States (U.S)
Keyskills:
physical design, icc, eda tools, cadence encounter, innovus, place & route,...
Job Description: Experience Level: 3 to 12 Years;Process node experience to be in the range of 28nm & below (i.e ...
Not disclosed
Posted by Amit Hotkar , 13 days ago
Infinity HR Consulting Pvt Ltd. 5-10 yrs Bengaluru
Keyskills:
Timing Closure, Static Timing Analysis, Project Management, STA...
Job Description: - Desirable experience in formal / logic equivalence checking techniques;- Must have at least 5 - 8 ...
Not disclosed
Posted by HR , 4 days ago
Catalyst 7-12 yrs Bengaluru
Keyskills:
Physical Design, Timing Closure, Timing Analysis, Signal Integrity...
Job Description: degree in Electrical Engineer, Computer Engineering or Computer Science with at least 14+ years of ASIC ...
Not disclosed
Posted by HR , 26 days ago
Vhunt4U 10-15 yrs Hyderabad, Bengaluru, Noida, Malaysia, Singapore
Keyskills:
DRC, Timing Closure, Primetime, Floor Planning, Static Timing Analysis...
Job Description: " Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, ...
Not disclosed
Posted by HR , Today

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eInfochips Limited 8-13 yrs Bengaluru
Keyskills:
Physical Design, Timing Closure, Floorplan, Placement, Signal Integrity...
Job Description: This job involves good written and verbal skills;Technically sound & good team player;Preferred Tool ...
Not disclosed
Posted by Shikha Singh , 12 days ago
Infinity HR Consulting Services 3-8 yrs Bengaluru
Keyskills:
Timing Closure, Physical Design, STA, Timing Analysis, Synthesis...
Job Description: - hands-on experience in timing analysis;- Experience in doing SoC level timing analysis;- Should be ...
Not disclosed
Posted by HR , 18 days ago
Shell Info Technologies Private Limited 3.8(10 reviews) 3-8 yrs Bengaluru, Chennai
Keyskills:
Verilog, VHDL, RTL Design, ASIC Design, VLSI, Ahb, Lec, Primetime, Axi...
Not disclosed
Posted by Jacintha. J , 4 days ago
Confidential 4-9 yrs Bengaluru
Keyskills:
Timing Closure, Physical Design, DRC, LVS, Physical Verification...
Job Description: - Expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep ...
Not disclosed
Posted by HR , 30+ days ago
Catalyst 7-12 yrs Bengaluru
Keyskills:
Static Timing Analysis, Primetime, STA, RTL Design, Timing Closure...
Job Description: He should be able to mentor young team member in addition to contribution as Individual contributor ...
Not disclosed
Posted by HR , 26 days ago
Core Edge Solutions 7-12 yrs Bengaluru
Keyskills:
System Verilog, UVM, OVM, VMM, Formal Verification, ASIC Design...
Job Description: This position requires at least 8 yrs of relevant industry experience;Prior Experience of verification ...
Not disclosed
Posted by Sheetal , 30+ days ago
Enlist Management Consultants 5-10 yrs Bengaluru
Keyskills:
PNR, Timing Closure, Physical Design, DRC, Timing Analysis, LVS, STA...
Job Description: Notice : Should be willing to join in 45 days max;- Prior experience with 28nm or lower technology nodes ...
Not disclosed
Posted by Mohammed Parvez , Today
Career Maker 9-13 yrs Bengaluru
Keyskills:
Verilog, VHDL, FPGA Design, RTL Design, ASIC, Synthesis, Timing Closure...
Job Description: Experience : 8 to 12 years of experience in reputed product based Semi conductor companies;- Prior RTL ...
Not disclosed
Posted by HR , 25 days ago
eInfochips Limited 8-13 yrs Bengaluru
Keyskills:
physical design, timing closure, floorplan, placement, tcl, icc, routing...
Job Description: This job involves good written and verbal skills;Technically sound & good team player;Preferred Tool ...
Not disclosed
Posted by Shikha Singh , Today
eInfochips Limited 3-6 yrs Bengaluru, Hyderabad
Keyskills:
Physical Design, Floorplan, Timing Closure, Placement, TCL...
Job Description: This job involves good written and verbal skills;Technically sound & good team player;Preferred Tool ...
Not disclosed
Posted by Flemy John , 13 days ago
SPICAWORKS INDIA PRIVATE LIMITED 4-9 yrs Bengaluru, Hyderabad, Delhi NCR
Keyskills:
DFT, Atpg, Bist, STA, Perl, Synthesis, JTAG, Timing Closure, Logic Design...
Job Description: Prior experience with post-silicon debug is an added advantage;Relevant industry experience in the field ...
Not disclosed
Posted by MANJULA SAHADEVA , 20 days ago
S.A.W IT Services Pvt Ltd 5-10 yrs Bengaluru
Keyskills:
DRC, STA, Timing Closure, RTL Design, Synthesis, LVS, Design Engineering...
Job Description: - Prior experience handling extremely area and power sensitive designs;- Power Network Analysis and fix ...
Not disclosed
Posted by Basheer , 30+ days ago
Infinity HR Consulting Services 7-12 yrs Bengaluru
Keyskills:
Verilog, VHDL, C, FPGA, Altera, Xilinx ISE, RTL Design, Timing Closure...
Job Description: - Experience with logic synthesis and floor planning tools (Synopsis, Cadence);- Experience with ...
Not disclosed
Posted by HR , 30+ days ago
CAREER MAKERS 9-13 yrs Bengaluru
Keyskills:
Verilog, VHDL, FPGA Design, RTL Design, ASIC, Synthesis, Timing Closure...
Job Description: Experience : 8 to 12 years of experience in reputed product based Semi conductor companies;- Prior RTL ...
Not disclosed
Posted by Not Provided , 28 days ago
Radiant Semiconductors Pvt Ltd 3-8 yrs Bengaluru(Kundalahalli)
Keyskills:
routing, DRC, MM, MC, DSM, LVS, physical design, place & route...
Job Description: Should have done similar job well in the past;Should have very good idea about OCV/MM/MC and multi power ...
Not disclosed
Posted by Radiant Semiconductors , 13 days ago
Catalyst 10-16 yrs Bengaluru
Keyskills:
Primetime, Timing Analysis, Physical Design, Timing Closure...
Job Description: degree in Electrical Engineer, Computer Engineering or Computer Science with at least 14+ years of ASIC ...
Not disclosed
Posted by HR , 27 days ago
Synopsys India Pvt. Ltd 4.1(36 reviews) 5-10 yrs Bengaluru, South Korea
Keyskills:
timing closure, physical design, floor planning, design engineering, PNR...
Job Description: Ability to close designs at advanced nodes like 14nm/10nm or below is required;- Should have good ...
Not disclosed
Posted by Akshat Chauhan , 11 days ago
Career Maker 5-10 yrs Bengaluru
Keyskills:
PNR, Physical Design, Timing Closure, STA, DRC, Floor Planning, LVS...
Job Description: - Well versed with the level timing closure (STA), timing closure methodologies, ECO generation and ...
Not disclosed
Posted by HR , 25 days ago
Intel Technology India Pvt Ltd 4.3(110 reviews) 3-8 yrs Bengaluru
Keyskills:
Physical Design, Synopsys Design Compiler, CPF, Synopsys ICC2...
Job Description: 3 - 15 years of PD experience in back-end design and/or integration;The ideal candidate should exhibit ...
Not disclosed
Posted by HR , 27 days ago
SPICAWORKS INDIA PRIVATE LIMITED 3-8 yrs Bengaluru
Keyskills:
timing closure, physical design, physical verification, icc, synopsys, cmos...
Job Description: Hands-on experience in block level and top level closure;Design experience in all aspects of physical ...
Not disclosed
Posted by MANJULA SAHADEVA , 30+ days ago
Invecas technologies Pvt Ltd 9-14 yrs Bengaluru, Hyderabad, Noida
Keyskills:
PNR, Physical Design, Floorplan, Placement, Floor Planning, Perl, TCL...
Job Description: Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting ...
Not disclosed
Posted by Asritha R , 30+ days ago
Global Technologies 4.4(15 reviews) 10-15 yrs Bengaluru
Keyskills:
PNR, Timing Closure, STA, Physical Design, Floor Planning, GDS, Synopsys...
Job Description: - Good knowledge of standard cell libraries - circuit design and cell layout;- Node experience upto 7nm, ...
Not disclosed
Posted by HR , 15 days ago
eInfochips Limited 10-15 yrs Bengaluru
Keyskills:
Physical Design, Timing Closure, Floorplan, Placement, Signal Integrity...
Job Description: This job involves good written and verbal skills;Technically sound & good team player;Preferred Tool ...
Not disclosed
Posted by Flemy John , 13 days ago
S.A.W IT Services Pvt Ltd 10-14 yrs Bengaluru
Keyskills:
DRC, Physical Design, Timing Closure, Floor Planning, Primetime...
Job Description: - Experience on top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, ...
Not disclosed
Posted by Basheer , 21 days ago
Global Technologies 4.4(15 reviews) 6-11 yrs Bengaluru
Keyskills:
Timing Closure, Physical Design, STA, Floor Planning, TCL, PNR, GDSII, CHIP
Job Description: Netlist to GDSII at block level, Subsystem Level and at Full chip. Worked on multipletapeoutson ...
Not disclosed
Posted by Nagesh , 22 days ago
Synapse Techno Design Innovations Pvt Ltd 3-8 yrs Bengaluru
Keyskills:
STA, Timing Closure, Static Timing Analysis, Perl, TCL, Synopsys, Synthesis...
Job Description: Successful tape out experience of multiple complex chips at 65 or 45 ...
Not disclosed
Posted by Amit Hotkar , 13 days ago
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